[llvm] fba0822 - [X86] Fold FMSUBADD into VFCMULC for fp16 complex conjugate multiply (#224533)
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Wed Sep 23 00:32:44 PDT 2026
Author: Rohan Shenoy
Date: 2026-09-23T07:32:37Z
New Revision: fba0822290721dd8144708d6c28902a87e3bb830
URL: https://github.com/llvm/llvm-project/commit/fba0822290721dd8144708d6c28902a87e3bb830
DIFF: https://github.com/llvm/llvm-project/commit/fba0822290721dd8144708d6c28902a87e3bb830.diff
LOG: [X86] Fold FMSUBADD into VFCMULC for fp16 complex conjugate multiply (#224533)
We reuse isCFMulFromFMSUBADD from #222896 to fold vfmsubadd into vfcmulc.
As a result using this pattern-match in combineFaddCFmul becomes
redundant as it (c += a * ~b) still becomes vfcmaddcph through the
existing fadd + vfcmulc combine.
Added:
llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a7cfd659868c2..3671d3b268218 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -56214,7 +56214,7 @@ static SDValue combineFMulcFCMulc(SDNode *N, SelectionDAG &DAG,
}
// We try to match the following pattern from FMSUBADD(X, A, M) to lower it
-// into complex conjugate fmadd for fp16 (#216290).
+// into complex conjugate multiply for fp16.
// for vector of the complex form v <v0r, v0i, v1r, v1i, ...>
// and 2 complex vectors a, b,
// X = duplicate real (b) : <b0r, b0r, b1r, b1r, ...>
@@ -56281,17 +56281,8 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
bool IsConj;
SDValue FAddOp1, MulOp0, MulOp1;
MVT CVT = MVT::getVectorVT(MVT::f32, VT.getVectorNumElements() / 2);
- auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj, &DAG,
- &IsVectorAllNegativeZero, &CVT](SDValue N) -> bool {
- if (N.getOpcode() == X86ISD::FMSUBADD && N.hasOneUse()) {
- SDValue A, B;
- if (!isCFMulFromFMSUBADD(N, DAG, A, B))
- return false;
- IsConj = true;
- MulOp0 = DAG.getBitcast(CVT, A);
- MulOp1 = DAG.getBitcast(CVT, B);
- return true;
- }
+ auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj,
+ &IsVectorAllNegativeZero](SDValue N) -> bool {
if (!N.hasOneUse() || N.getOpcode() != ISD::BITCAST)
return false;
SDValue Op0 = N.getOperand(0);
@@ -58556,18 +58547,37 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
}
}
+// Combine FMSUBADD(SHUFFLE(B),A,FMUL(SHUFFLE(A),SHUFFLE(B))) -> VFCMULC(A,B)
// Combine FMADDSUB(A, B, FNEG(C)) -> FMSUBADD(A, B, C)
// Combine FMSUBADD(A, B, FNEG(C)) -> FMADDSUB(A, B, C)
static SDValue combineFMADDSUB(SDNode *N, SelectionDAG &DAG,
- TargetLowering::DAGCombinerInfo &DCI) {
+ TargetLowering::DAGCombinerInfo &DCI,
+ const X86Subtarget &Subtarget) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
+ SDValue N2 = N->getOperand(2);
+
+ if (N->getOpcode() == X86ISD::FMSUBADD && Subtarget.hasFP16() &&
+ N->hasOneUse() &&
+ (VT == MVT::v8f16 || VT == MVT::v16f16 || VT == MVT::v32f16)) {
+ SDValue A, B;
+ if (isCFMulFromFMSUBADD(SDValue(N, 0), DAG, A, B)) {
+ MVT CVT = MVT::getVectorVT(MVT::f32, VT.getVectorNumElements() / 2);
+ SDValue MulOp0 = DAG.getBitcast(CVT, A);
+ SDValue MulOp1 = DAG.getBitcast(CVT, B);
+ // FMSUBADD has no flags, so we use the flags from the FMUL (i.e. the
+ // third operand) it was fused from, as it is the only operand which
+ // still has FMF (see isCFMulFromFMSUBADD for the pattern).
+ SDValue Fmulc =
+ DAG.getNode(X86ISD::VFCMULC, dl, CVT, MulOp0, MulOp1, N2->getFlags());
+ return DAG.getBitcast(VT, Fmulc);
+ }
+ }
+
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
bool CodeSize = DAG.getMachineFunction().getFunction().hasOptSize();
bool LegalOperations = !DCI.isBeforeLegalizeOps();
- SDValue N2 = N->getOperand(2);
-
SDValue NegN2 =
TLI.getCheaperNegatedExpression(N2, DAG, LegalOperations, CodeSize);
if (!NegN2)
@@ -64225,7 +64235,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::FMADDSUB_RND:
case X86ISD::FMSUBADD_RND:
case X86ISD::FMADDSUB:
- case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, DCI);
+ case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, DCI, Subtarget);
case X86ISD::MOVMSK: return combineMOVMSK(N, DAG, DCI, Subtarget);
case X86ISD::TESTP: return combineTESTP(N, DAG, DCI, Subtarget);
case X86ISD::MGATHER:
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
new file mode 100644
index 0000000000000..c2ff3c51b5705
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s
+
+define <8 x half> @test_128(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: test_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcmulcph %xmm1, %xmm0, %xmm2
+; CHECK-NEXT: vmovaps %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %dup_even_b = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
+ %mul_re = fmul contract <8 x half> %a, %dup_even_b
+ %swap_a = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+ %dup_odd_b = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
+ %mul_im = fmul contract <8 x half> %swap_a, %dup_odd_b
+ %add = fadd contract <8 x half> %mul_re, %mul_im
+ %sub = fsub contract <8 x half> %mul_re, %mul_im
+ %cmul = shufflevector <8 x half> %add, <8 x half> %sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+ ret <8 x half> %cmul
+}
+
+define <16 x half> @test_256(<16 x half> %a, <16 x half> %b) {
+; CHECK-LABEL: test_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcmulcph %ymm1, %ymm0, %ymm2
+; CHECK-NEXT: vmovaps %ymm2, %ymm0
+; CHECK-NEXT: retq
+ %dup_even_b = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
+ %mul_re = fmul contract <16 x half> %dup_even_b, %a
+ %swap_a = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
+ %dup_odd_b = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
+ %mul_im = fmul contract <16 x half> %dup_odd_b, %swap_a
+ %add = fadd contract <16 x half> %mul_re, %mul_im
+ %sub = fsub contract <16 x half> %mul_re, %mul_im
+ %cmul = shufflevector <16 x half> %add, <16 x half> %sub, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+ ret <16 x half> %cmul
+}
+
+define <32 x half> @test_512(<32 x half> %a, <32 x half> %b) {
+; CHECK-LABEL: test_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vfcmulcph %zmm1, %zmm0, %zmm2
+; CHECK-NEXT: vmovaps %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %dup_even_b = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14, i32 16, i32 16, i32 18, i32 18, i32 20, i32 20, i32 22, i32 22, i32 24, i32 24, i32 26, i32 26, i32 28, i32 28, i32 30, i32 30>
+ %mul_re = fmul contract <32 x half> %dup_even_b, %a
+ %swap_a = shufflevector <32 x half> %a, <32 x half> poison, <32 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14, i32 17, i32 16, i32 19, i32 18, i32 21, i32 20, i32 23, i32 22, i32 25, i32 24, i32 27, i32 26, i32 29, i32 28, i32 31, i32 30>
+ %dup_odd_b = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15, i32 17, i32 17, i32 19, i32 19, i32 21, i32 21, i32 23, i32 23, i32 25, i32 25, i32 27, i32 27, i32 29, i32 29, i32 31, i32 31>
+ %mul_im = fmul contract <32 x half> %swap_a, %dup_odd_b
+ %add = fadd contract <32 x half> %mul_re, %mul_im
+ %sub = fsub contract <32 x half> %mul_re, %mul_im
+ %cmul = shufflevector <32 x half> %add, <32 x half> %sub, <32 x i32> <i32 0, i32 33, i32 2, i32 35, i32 4, i32 37, i32 6, i32 39, i32 8, i32 41, i32 10, i32 43, i32 12, i32 45, i32 14, i32 47, i32 16, i32 49, i32 18, i32 51, i32 20, i32 53, i32 22, i32 55, i32 24, i32 57, i32 26, i32 59, i32 28, i32 61, i32 30, i32 63>
+ ret <32 x half> %cmul
+}
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