[llvm] [SPIR-V] Fix ldexp exponent splat for vectors wider than four elements (PR #225617)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/225617

The shared createVirtualRegister helper sets the full vector LLT, which does not match the 128-bit vector register classes and trips a size assert

>From f88cb4969c138b87558dc618969b140cb9de6805 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 23 Sep 2026 09:18:25 +0200
Subject: [PATCH] [SPIR-V] Fix ldexp exponent splat for vectors wider than four
 elements

The shared createVirtualRegister helper sets the full vector LLT, which does not match the 128-bit vector register classes and trips a size assert
---
 llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp |  4 ++--
 llvm/test/CodeGen/SPIRV/llvm-intrinsics/ldexp.ll   | 12 ++++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 0ea9e552ce2e3a..9a9ca0107d1c9a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -1685,8 +1685,8 @@ bool SPIRVInstructionSelector::selectLdexp(Register ResVReg,
     unsigned NumElts = ResType->getOperand(2).getImm();
     SPIRVTypeInst ExpVecType =
         GR.getOrCreateSPIRVVectorType(ExpType, NumElts, I, TII);
-    Register SplatReg =
-        createVirtualRegister(ExpVecType, &GR, MRI, MRI->getMF());
+    Register SplatReg = MRI->createVirtualRegister(GR.getRegClass(ExpVecType));
+    GR.assignSPIRVTypeToVReg(ExpVecType, SplatReg, MRI->getMF());
     auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
                        TII.get(SPIRV::OpCompositeConstruct))
                    .addDef(SplatReg)
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ldexp.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ldexp.ll
index d963c72190781b..bf0d8e28f74757 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ldexp.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ldexp.ll
@@ -10,6 +10,8 @@
 ; CHECK-DAG: %[[#Int32:]] = OpTypeInt 32 0
 ; CHECK-DAG: %[[#Float4:]] = OpTypeVector %[[#Float]] 4
 ; CHECK-DAG: %[[#Int4:]] = OpTypeVector %[[#Int32]] 4
+; CHECK-DAG: %[[#Float8:]] = OpTypeVector %[[#Float]] 8
+; CHECK-DAG: %[[#Int8:]] = OpTypeVector %[[#Int32]] 8
 
 define spir_func void @test_ldexp(ptr %xh, ptr %xf, ptr %xd, ptr %xv,
                                   half %h, float %f, double %d, <4 x float> %vf,
@@ -31,7 +33,17 @@ entry:
   ret void
 }
 
+define spir_func void @test_ldexp_v8(ptr %xv, <8 x float> %vf, i32 %k) {
+entry:
+  %0 = call <8 x float> @llvm.ldexp.v8f32.i32(<8 x float> %vf, i32 %k)
+  store <8 x float> %0, ptr %xv
+; CHECK: %[[#Splat8:]] = OpCompositeConstruct %[[#Int8]]
+; CHECK: %[[#]] = OpExtInst %[[#Float8]] %[[#ExtInstSetId]] ldexp %[[#]] %[[#Splat8]]
+  ret void
+}
+
 declare half @llvm.ldexp.f16.i32(half, i32)
 declare float @llvm.ldexp.f32.i32(float, i32)
 declare double @llvm.ldexp.f64.i32(double, i32)
 declare <4 x float> @llvm.ldexp.v4f32.i32(<4 x float>, i32)
+declare <8 x float> @llvm.ldexp.v8f32.i32(<8 x float>, i32)