[llvm] [Target] Remove declarations without definitions (NFC) (PR #225615)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 00:17:44 PDT 2026
https://github.com/kazutakahirata created https://github.com/llvm/llvm-project/pull/225615
initializeAArch64CFIFixupPass: Added on April 11, 2022 in commit
b4ad28da196d3c2b1bc064b4dc46c3e00e93438f without a definition.
AArch64InstructionSelector::selectReduction: The definition was removed
on November 13, 2023 in commit a604c4b562e99470e397f050f1e8707f923ebed7.
AArch64TargetELFStreamer::insertAttributeInPlace: Added on January 23,
2025 in commit ee99c4d4845db66c4daa2373352133f4b237c942 without a
definition.
ARMInstPrinter::printAM2PostIndexOp: The definition was removed on
September 22, 2012 in commit 2fdbdc58701ef41ab6b52c064723926e6ec4b44f.
ARMMCCodeEmitter::getMachineSoImmOpValue: The definition was removed on
October 12, 2010 in commit 12e493ace4fc5b499361122bc5f25d2c46bea5e4.
ARMMCCodeEmitter::getThumbSRImmOpValue: The definition was removed on
August 17, 2011 in commit 46dd413991f6fa74a1da3f139b386e364dfc9f78.
createAVRBranchSelectionPass: The definition was removed on July 5, 2017
in commit a24aa1990084c15f0ad27dbcff7ab1c96369f0f9.
dxil::DXILOpBuilder::getOpFunctionType: Added on August 2, 2024 in
commit 8cf85653b6f5c90b83f8a5741baad5725d6c6932 without a definition.
dxil::DXILBitcodeWriter::VSTOffsetPlaceholder,
dxil::DXILBitcodeWriter::writeIdentificationBlock,
dxil::DXILBitcodeWriter::writePerModuleFunctionSummaryRecord,
dxil::DXILBitcodeWriter::writeModuleLevelReferences,
dxil::DXILBitcodeWriter::addToStrtab,
dxil::DXILBitcodeWriter::createNamedMetadataAbbrev,
dxil::DXILBitcodeWriter::writeNamedMetadata,
dxil::DXILBitcodeWriter::pushGlobalMetadataAttachment,
dxil::DXILBitcodeWriter::writeOperandBundleTags,
dxil::DXILBitcodeWriter::writeSyncScopeNames,
dxil::DXILBitcodeWriter::writeOperandBundles,
dxil::DXILBitcodeWriter::writeGlobalValueSymbolTable: Added on
April 14, 2022 in commit f2526c1a5c6fe6d2740b68e2d73b85c958fd2719
without uses or definitions.
initializeHexagonMergeActivateWeightPass,
createHexagonMergeActivateWeight: Added on August 5, 2024 in commit
c04857cb2c9f6f2e8add61192c62e48a83938efd without definitions.
createHexagonTargetTransformInfoPass: Added on June 15, 2015 in commit
56efafc0566def51ec7e632e09574ed553296b48 without a definition.
HexagonGlobalSchedulerImpl::CanPromoteToDotNew: Added on February 20,
2026 in commit 7064ff2226141034fdb264c29b97acbc733f8dae without a
definition.
HexagonTargetLowering::LowerANY_EXTEND,
HexagonTargetLowering::LowerSIGN_EXTEND,
HexagonTargetLowering::LowerZERO_EXTEND: The definitions were removed on
February 6, 2018 in commit 8abaf8954a97f20d0fd036e8e32e4b69d23f342e.
HexagonTargetLowering::LowerEH_LABEL: Added on December 12, 2011 in
commit 1213a7a57fdcb6c875b3f79103fc96d3e9d30b40 without a definition.
HexagonPacketizerList::isCurifiable: Added on December 16, 2015 in
commit 56bbf54b4303cac8772b6d66e3bd0668f8013067 without a definition.
HexagonMCChecker::checkBranches: The definition was removed on
December 11, 2017 in commit a8ab1b75cb0d84ea61642d7b7c0139e6e367c28e.
createHexagonMCRegisterInfo: Added on February 6, 2017 in commit
8cdfe8ecf3dd14d128148c5ff0b01d74b082e3c2 without a definition.
HexagonShuffler::restrictNoSlot1: Added on January 17, 2020 in commit
c1873631d0a8f2acca4ab428a1e9abea844d97ff without a definition.
MipsAsmParser::parseImm: The definition was removed on August 8, 2016 in
commit 3feeb9c851a193f42d890b35f36816fae198860f.
MipsAsmParser::validateMSAIndex: The definition was removed on April 1,
2014 in commit b50ccf8e26653781191491aab90c7379f29bd5e1.
MipsMCCodeEmitter::getMSAMemEncoding: The definition was removed on
March 31, 2016 in commit dc0602a2c20a3f514541165a19cb1534597c5dc6.
Mips16DAGToDAGISel::initMips16SPAliasReg: The definition was removed on
June 16, 2016 in commit de7816b0cd3ffbd9775681c408298febe4c10fe3.
MipsAsmPrinter::EmitInstrWithMacroNoAT: The definition was removed on
June 2, 2012 in commit 23327b30ef9af2323dd20248e311ef454f9e0dfa.
MipsTargetLowering::emitSEL_D: The definition was removed on July 20,
2017 in commit be0bc71e023455a32d074b69054b6ffee6f1160e.
MipsSEDAGToDAGISel::selectMULT: The definition was removed on April 11,
2013 in commit 4f1130eb66ff01128c0061ace377c10b74128a45.
MipsSETargetLowering::lowerINT_TO_FP,
MipsSETargetLowering::lowerFP_TO_INT: The definitions were removed on
June 17, 2026 in commit de84e7ccc602fe2ef8b886a9b095c80d110f61a0.
MipsSubtarget::IsLinux: All uses were removed on December 19, 2014 in
commit 8985ba912f00de68f3fccf8bf440a30bf5bdb89e.
MipsSubtarget::OverrideMode, MipsSubtarget::setHelperClassesMips16,
MipsSubtarget::setHelperClassesMipsSE: All uses of OverrideMode and the
definitions of setHelperClassesMips16 and setHelperClassesMipsSE were
removed on July 18, 2014 in commit
4e7d1e7e7bb36bcd715297b36d688bdc0ed96bdf.
initializeNVVMReflectPass: The definition was removed on April 10, 2025
in commit 701d726ef09ea89909df9bd2fdc63c63758fe8d6.
NVPTXDAGToDAGISel::SelectTexSurfHandle: The definition was removed on
June 25, 2025 in commit 70333de6cfa76d2e0e36720d6065edd501a3ad8a.
NVPTXDAGToDAGISel::tryConstantFP: The definition was removed on
December 19, 2024 in commit 310e79875752886a7713911e2a1ec14bc75bd4b3.
NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorReduceCommon: The definition
was removed on August 6, 2026 in commit
1ac19e41a0674925911e88cc5218dfd95a09a3ac.
createPPCMachObjectWriter: The definition was removed on March 2, 2020
in commit 3e851f4a688c42315355aae743b403dddeba9860.
createPPCExpandISELPass: The definition was removed on August 27, 2024
in commit 8e901c255df45e38cb1d69a576804029e20868bf.
SystemZTargetLowering::convertPrevCompareToBranch: The definition was
removed on July 25, 2013 in commit
c3f85d73ab781601b2aababa8ef6572fa437c4ff.
VEAsmParser::parseCCOpOperand: Added on June 5, 2020 in commit
117c0d7c1c12e5c82e0f5498fec511e8ae08d9ca without a definition.
VEAsmParser::parseRDOpOperand: Added on June 10, 2020 in commit
34fef0c980446c3ea9595328e0e525db222870f0 without a definition.
WebAssemblyOptimizeReturnedLegacy::visitCallBase: The definition was
moved to a helper class on July 15, 2026 in commit
491539a8b801aad5706cc32fc54a319791d57a91.
X86FixupInstTuningLegacy::processInstruction: The definition was moved
to a helper class on January 12, 2026 in commit
f6d0a512972a74ef100723b9526a6a0ddb23f894.
XCoreTargetLowering::getReturnAddressFrameIndex: Added on November 7,
2008 in commit ca08e0645a9629980156208506b6ae463b746e42 without a
definition.
Assisted-by: Antigravity
>From b2e9fd29af810513e0d2643c1a84573d44c0c1f3 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sat, 19 Sep 2026 16:50:41 -0700
Subject: [PATCH] [Target] Remove declarations without definitions (NFC)
initializeAArch64CFIFixupPass: Added on April 11, 2022 in commit
b4ad28da196d3c2b1bc064b4dc46c3e00e93438f without a definition.
AArch64InstructionSelector::selectReduction: The definition was removed
on November 13, 2023 in commit a604c4b562e99470e397f050f1e8707f923ebed7.
AArch64TargetELFStreamer::insertAttributeInPlace: Added on January 23,
2025 in commit ee99c4d4845db66c4daa2373352133f4b237c942 without a
definition.
ARMInstPrinter::printAM2PostIndexOp: The definition was removed on
September 22, 2012 in commit 2fdbdc58701ef41ab6b52c064723926e6ec4b44f.
ARMMCCodeEmitter::getMachineSoImmOpValue: The definition was removed on
October 12, 2010 in commit 12e493ace4fc5b499361122bc5f25d2c46bea5e4.
ARMMCCodeEmitter::getThumbSRImmOpValue: The definition was removed on
August 17, 2011 in commit 46dd413991f6fa74a1da3f139b386e364dfc9f78.
createAVRBranchSelectionPass: The definition was removed on July 5, 2017
in commit a24aa1990084c15f0ad27dbcff7ab1c96369f0f9.
dxil::DXILOpBuilder::getOpFunctionType: Added on August 2, 2024 in
commit 8cf85653b6f5c90b83f8a5741baad5725d6c6932 without a definition.
dxil::DXILBitcodeWriter::VSTOffsetPlaceholder,
dxil::DXILBitcodeWriter::writeIdentificationBlock,
dxil::DXILBitcodeWriter::writePerModuleFunctionSummaryRecord,
dxil::DXILBitcodeWriter::writeModuleLevelReferences,
dxil::DXILBitcodeWriter::addToStrtab,
dxil::DXILBitcodeWriter::createNamedMetadataAbbrev,
dxil::DXILBitcodeWriter::writeNamedMetadata,
dxil::DXILBitcodeWriter::pushGlobalMetadataAttachment,
dxil::DXILBitcodeWriter::writeOperandBundleTags,
dxil::DXILBitcodeWriter::writeSyncScopeNames,
dxil::DXILBitcodeWriter::writeOperandBundles,
dxil::DXILBitcodeWriter::writeGlobalValueSymbolTable: Added on
April 14, 2022 in commit f2526c1a5c6fe6d2740b68e2d73b85c958fd2719
without uses or definitions.
initializeHexagonMergeActivateWeightPass,
createHexagonMergeActivateWeight: Added on August 5, 2024 in commit
c04857cb2c9f6f2e8add61192c62e48a83938efd without definitions.
createHexagonTargetTransformInfoPass: Added on June 15, 2015 in commit
56efafc0566def51ec7e632e09574ed553296b48 without a definition.
HexagonGlobalSchedulerImpl::CanPromoteToDotNew: Added on February 20,
2026 in commit 7064ff2226141034fdb264c29b97acbc733f8dae without a
definition.
HexagonTargetLowering::LowerANY_EXTEND,
HexagonTargetLowering::LowerSIGN_EXTEND,
HexagonTargetLowering::LowerZERO_EXTEND: The definitions were removed on
February 6, 2018 in commit 8abaf8954a97f20d0fd036e8e32e4b69d23f342e.
HexagonTargetLowering::LowerEH_LABEL: Added on December 12, 2011 in
commit 1213a7a57fdcb6c875b3f79103fc96d3e9d30b40 without a definition.
HexagonPacketizerList::isCurifiable: Added on December 16, 2015 in
commit 56bbf54b4303cac8772b6d66e3bd0668f8013067 without a definition.
HexagonMCChecker::checkBranches: The definition was removed on
December 11, 2017 in commit a8ab1b75cb0d84ea61642d7b7c0139e6e367c28e.
createHexagonMCRegisterInfo: Added on February 6, 2017 in commit
8cdfe8ecf3dd14d128148c5ff0b01d74b082e3c2 without a definition.
HexagonShuffler::restrictNoSlot1: Added on January 17, 2020 in commit
c1873631d0a8f2acca4ab428a1e9abea844d97ff without a definition.
MipsAsmParser::parseImm: The definition was removed on August 8, 2016 in
commit 3feeb9c851a193f42d890b35f36816fae198860f.
MipsAsmParser::validateMSAIndex: The definition was removed on April 1,
2014 in commit b50ccf8e26653781191491aab90c7379f29bd5e1.
MipsMCCodeEmitter::getMSAMemEncoding: The definition was removed on
March 31, 2016 in commit dc0602a2c20a3f514541165a19cb1534597c5dc6.
Mips16DAGToDAGISel::initMips16SPAliasReg: The definition was removed on
June 16, 2016 in commit de7816b0cd3ffbd9775681c408298febe4c10fe3.
MipsAsmPrinter::EmitInstrWithMacroNoAT: The definition was removed on
June 2, 2012 in commit 23327b30ef9af2323dd20248e311ef454f9e0dfa.
MipsTargetLowering::emitSEL_D: The definition was removed on July 20,
2017 in commit be0bc71e023455a32d074b69054b6ffee6f1160e.
MipsSEDAGToDAGISel::selectMULT: The definition was removed on April 11,
2013 in commit 4f1130eb66ff01128c0061ace377c10b74128a45.
MipsSETargetLowering::lowerINT_TO_FP,
MipsSETargetLowering::lowerFP_TO_INT: The definitions were removed on
June 17, 2026 in commit de84e7ccc602fe2ef8b886a9b095c80d110f61a0.
MipsSubtarget::IsLinux: All uses were removed on December 19, 2014 in
commit 8985ba912f00de68f3fccf8bf440a30bf5bdb89e.
MipsSubtarget::OverrideMode, MipsSubtarget::setHelperClassesMips16,
MipsSubtarget::setHelperClassesMipsSE: All uses of OverrideMode and the
definitions of setHelperClassesMips16 and setHelperClassesMipsSE were
removed on July 18, 2014 in commit
4e7d1e7e7bb36bcd715297b36d688bdc0ed96bdf.
initializeNVVMReflectPass: The definition was removed on April 10, 2025
in commit 701d726ef09ea89909df9bd2fdc63c63758fe8d6.
NVPTXDAGToDAGISel::SelectTexSurfHandle: The definition was removed on
June 25, 2025 in commit 70333de6cfa76d2e0e36720d6065edd501a3ad8a.
NVPTXDAGToDAGISel::tryConstantFP: The definition was removed on
December 19, 2024 in commit 310e79875752886a7713911e2a1ec14bc75bd4b3.
NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorReduceCommon: The definition
was removed on August 6, 2026 in commit
1ac19e41a0674925911e88cc5218dfd95a09a3ac.
createPPCMachObjectWriter: The definition was removed on March 2, 2020
in commit 3e851f4a688c42315355aae743b403dddeba9860.
createPPCExpandISELPass: The definition was removed on August 27, 2024
in commit 8e901c255df45e38cb1d69a576804029e20868bf.
SystemZTargetLowering::convertPrevCompareToBranch: The definition was
removed on July 25, 2013 in commit
c3f85d73ab781601b2aababa8ef6572fa437c4ff.
VEAsmParser::parseCCOpOperand: Added on June 5, 2020 in commit
117c0d7c1c12e5c82e0f5498fec511e8ae08d9ca without a definition.
VEAsmParser::parseRDOpOperand: Added on June 10, 2020 in commit
34fef0c980446c3ea9595328e0e525db222870f0 without a definition.
WebAssemblyOptimizeReturnedLegacy::visitCallBase: The definition was
moved to a helper class on July 15, 2026 in commit
491539a8b801aad5706cc32fc54a319791d57a91.
X86FixupInstTuningLegacy::processInstruction: The definition was moved
to a helper class on January 12, 2026 in commit
f6d0a512972a74ef100723b9526a6a0ddb23f894.
XCoreTargetLowering::getReturnAddressFrameIndex: Added on November 7,
2008 in commit ca08e0645a9629980156208506b6ae463b746e42 without a
definition.
Assisted-by: Antigravity
---
llvm/lib/Target/AArch64/AArch64.h | 1 -
.../GISel/AArch64InstructionSelector.cpp | 1 -
.../MCTargetDesc/AArch64TargetStreamer.h | 3 ---
.../Target/ARM/MCTargetDesc/ARMInstPrinter.h | 2 --
.../ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 6 -----
llvm/lib/Target/AVR/AVR.h | 1 -
llvm/lib/Target/DirectX/DXILOpBuilder.h | 5 ----
.../DirectX/DXILWriter/DXILBitcodeWriter.cpp | 27 -------------------
llvm/lib/Target/Hexagon/Hexagon.h | 6 -----
.../Target/Hexagon/HexagonGlobalScheduler.cpp | 2 --
llvm/lib/Target/Hexagon/HexagonISelLowering.h | 4 ---
.../Target/Hexagon/HexagonVLIWPacketizer.h | 1 -
.../Hexagon/MCTargetDesc/HexagonMCChecker.h | 1 -
.../MCTargetDesc/HexagonMCTargetDesc.h | 1 -
.../Hexagon/MCTargetDesc/HexagonShuffler.h | 1 -
.../Target/Mips/AsmParser/MipsAsmParser.cpp | 6 -----
.../Mips/MCTargetDesc/MipsMCCodeEmitter.h | 4 ---
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h | 2 --
llvm/lib/Target/Mips/MipsAsmPrinter.h | 2 --
llvm/lib/Target/Mips/MipsISelLowering.h | 1 -
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h | 4 ---
llvm/lib/Target/Mips/MipsSEISelLowering.h | 2 --
llvm/lib/Target/Mips/MipsSubtarget.h | 11 --------
llvm/lib/Target/NVPTX/NVPTX.h | 1 -
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 4 ---
.../PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 3 ---
llvm/lib/Target/PowerPC/PPC.h | 1 -
llvm/lib/Target/SystemZ/SystemZISelLowering.h | 9 -------
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp | 2 --
.../WebAssemblyOptimizeReturned.cpp | 2 --
llvm/lib/Target/X86/X86FixupInstTuning.cpp | 2 --
llvm/lib/Target/XCore/XCoreISelLowering.h | 1 -
32 files changed, 119 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index bcf40a02e3cf5a..da053420406975 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -168,7 +168,6 @@ void initializeAArch64AdvSIMDScalarLegacyPass(PassRegistry &);
void initializeAArch64AsmPrinterPass(PassRegistry &);
void initializeAArch64PointerAuthLegacyPass(PassRegistry &);
void initializeAArch64BranchTargetsLegacyPass(PassRegistry &);
-void initializeAArch64CFIFixupPass(PassRegistry&);
void initializeAArch64CollectLOHLegacyPass(PassRegistry &);
void initializeAArch64CompressJumpTablesLegacyPass(PassRegistry &);
void initializeAArch64CondBrTuningPass(PassRegistry &);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 55eb12460fc4f8..f42e1864d41b54 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -230,7 +230,6 @@ class AArch64InstructionSelector : public InstructionSelector {
bool selectTLSGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI);
bool selectPtrAuthGlobalValue(MachineInstr &I,
MachineRegisterInfo &MRI) const;
- bool selectReduction(MachineInstr &I, MachineRegisterInfo &MRI);
bool selectMOPS(MachineInstr &I, MachineRegisterInfo &MRI);
bool selectUSMovFromExtend(MachineInstr &I, MachineRegisterInfo &MRI);
void SelectTable(MachineInstr &I, MachineRegisterInfo &MRI, unsigned NumVecs,
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
index f840058cd759e9..1b3adeee7d38f0 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
@@ -112,9 +112,6 @@ class AArch64TargetStreamer : public MCTargetStreamer {
getActiveAttributesSubsection();
std::unique_ptr<MCELFStreamer::AttributeSubSection>
getAttributesSubsectionByName(StringRef Name);
- void
- insertAttributeInPlace(const MCELFStreamer::AttributeItem &Attr,
- MCELFStreamer::AttributeSubSection &AttSubSection);
SmallVector<MCELFStreamer::AttributeSubSection, 64> AttributeSubSections;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
index 7b95b9580740f3..3aa9045892076e 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
@@ -59,8 +59,6 @@ class ARMInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
- void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 9d58116548ac8a..06d4597b1aa1e3 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -71,8 +71,6 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
return TT.isOSBinFormatMachO();
}
- unsigned getMachineSoImmOpValue(unsigned SoImm) const;
-
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI,
@@ -380,10 +378,6 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h
index 68ec9271f75eac..5c9e3fb1b4a19f 100644
--- a/llvm/lib/Target/AVR/AVR.h
+++ b/llvm/lib/Target/AVR/AVR.h
@@ -29,7 +29,6 @@ Pass *createAVRShiftExpandPass();
FunctionPass *createAVRISelDag(AVRTargetMachine &TM, CodeGenOptLevel OptLevel);
FunctionPass *createAVRExpandPseudoPass();
FunctionPass *createAVRFrameAnalyzerPass();
-FunctionPass *createAVRBranchSelectionPass();
void initializeAVRAsmPrinterPass(PassRegistry &);
void initializeAVRDAGToDAGISelLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/DirectX/DXILOpBuilder.h b/llvm/lib/Target/DirectX/DXILOpBuilder.h
index 0985f2ee7cf1f5..66467152a53f10 100644
--- a/llvm/lib/Target/DirectX/DXILOpBuilder.h
+++ b/llvm/lib/Target/DirectX/DXILOpBuilder.h
@@ -66,11 +66,6 @@ class DXILOpBuilder {
static const char *getOpCodeName(dxil::OpCode DXILOp);
private:
- /// Gets a specific overload type of the function for the given DXIL op. If
- /// the operation is not overloaded, \c OverloadType may be nullptr.
- FunctionType *getOpFunctionType(dxil::OpCode OpCode,
- Type *OverloadType = nullptr);
-
Module &M;
IRBuilder<> IRB;
VersionTuple DXILVersion;
diff --git a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
index b58c34d07234be..a662b00fd6e5b4 100644
--- a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+++ b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
@@ -116,10 +116,6 @@ class DXILBitcodeWriter {
/// Tracks the last value id recorded in the GUIDToValueMap.
unsigned GlobalValueId;
- /// Saves the offset of the VSTOffset record that must eventually be
- /// backpatched with the offset of the actual VST.
- uint64_t VSTOffsetPlaceholder = 0;
-
/// Pointer to the buffer allocated by caller for bitcode writing.
const SmallVectorImpl<char> &Buffer;
@@ -155,7 +151,6 @@ class DXILBitcodeWriter {
static uint64_t getAttrKindEncoding(Attribute::AttrKind Kind);
static void writeStringRecord(BitstreamWriter &Stream, unsigned Code,
StringRef Str, unsigned AbbrevToUse);
- static void writeIdentificationBlock(BitstreamWriter &Stream);
static void emitSignedInt64(SmallVectorImpl<uint64_t> &Vals, uint64_t V);
static void emitWideAPInt(SmallVectorImpl<uint64_t> &Vals, const APInt &A);
@@ -176,17 +171,6 @@ class DXILBitcodeWriter {
void writeModuleVersion();
void writePerModuleGlobalValueSummary();
- void writePerModuleFunctionSummaryRecord(SmallVector<uint64_t, 64> &NameVals,
- GlobalValueSummary *Summary,
- unsigned ValueID,
- unsigned FSCallsAbbrev,
- unsigned FSCallsProfileAbbrev,
- const Function &F);
- void writeModuleLevelReferences(const GlobalVariable &V,
- SmallVector<uint64_t, 64> &NameVals,
- unsigned FSModRefsAbbrev,
- unsigned FSModVTableRefsAbbrev);
-
void assignValueId(GlobalValue::GUID ValGUID) {
GUIDToValueIdMap[ValGUID] = ++GlobalValueId;
}
@@ -211,8 +195,6 @@ class DXILBitcodeWriter {
uint64_t bitcodeStartBit() { return BitcodeStartBit; }
- size_t addToStrtab(StringRef Str);
-
unsigned createDILocationAbbrev();
unsigned createGenericDINodeAbbrev();
@@ -332,8 +314,6 @@ class DXILBitcodeWriter {
void writeDIImportedEntity(const DIImportedEntity *N,
SmallVectorImpl<uint64_t> &Record,
unsigned Abbrev);
- unsigned createNamedMetadataAbbrev();
- void writeNamedMetadata(SmallVectorImpl<uint64_t> &Record);
unsigned createMetadataStringsAbbrev();
void writeMetadataStrings(ArrayRef<const Metadata *> Strings,
SmallVectorImpl<uint64_t> &Record);
@@ -344,16 +324,11 @@ class DXILBitcodeWriter {
void writeModuleMetadata();
void writeFunctionMetadata(const Function &F);
void writeFunctionMetadataAttachment(const Function &F);
- void pushGlobalMetadataAttachment(SmallVectorImpl<uint64_t> &Record,
- const GlobalObject &GO);
void writeModuleMetadataKinds();
- void writeOperandBundleTags();
- void writeSyncScopeNames();
void writeConstants(unsigned FirstVal, unsigned LastVal, bool isGlobal);
void writeModuleConstants();
bool pushValueAndType(const Value *V, unsigned InstID,
SmallVectorImpl<unsigned> &Vals);
- void writeOperandBundles(const CallBase &CB, unsigned InstID);
void pushValue(const Value *V, unsigned InstID,
SmallVectorImpl<unsigned> &Vals);
void pushValueSigned(const Value *V, unsigned InstID,
@@ -361,8 +336,6 @@ class DXILBitcodeWriter {
void writeInstruction(const Instruction &I, unsigned InstID,
SmallVectorImpl<unsigned> &Vals);
void writeFunctionLevelValueSymbolTable(const ValueSymbolTable &VST);
- void writeGlobalValueSymbolTable(
- DenseMap<const Function *, uint64_t> &FunctionToBitcodeIndex);
void writeFunction(const Function &F);
void writeBlockInfo();
diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h
index b0e5041fb850a3..40ffef82d344df 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.h
+++ b/llvm/lib/Target/Hexagon/Hexagon.h
@@ -51,7 +51,6 @@ void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
void initializeHexagonLoopAlignPass(PassRegistry &);
void initializeHexagonLoopReschedulingPass(PassRegistry &);
void initializeHexagonMaskPass(PassRegistry &);
-void initializeHexagonMergeActivateWeightPass(PassRegistry &);
void initializeHexagonNewValueJumpPass(PassRegistry &);
void initializeHexagonOptAddrModePass(PassRegistry &);
void initializeHexagonPacketizerPass(PassRegistry &);
@@ -79,10 +78,6 @@ void initializeHexagonXQFloatGeneratorPass(PassRegistry &);
Pass *createHexagonLoopIdiomPass();
Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
-/// Creates a Hexagon-specific Target Transformation Info pass.
-ImmutablePass *
-createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM);
-
ModulePass *createHexagonAlignGlobalArrays(bool ReduceRodataSize);
FunctionPass *createHexagonBitSimplify();
@@ -109,7 +104,6 @@ FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
FunctionPass *createHexagonLoopAlign();
FunctionPass *createHexagonLoopRescheduling();
FunctionPass *createHexagonMask();
-FunctionPass *createHexagonMergeActivateWeight();
FunctionPass *createHexagonNewValueJump();
FunctionPass *createHexagonOptAddrMode();
FunctionPass *createHexagonOptimizeSZextends();
diff --git a/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
index 30b9b207b539bf..73ffb42914ad2e 100644
--- a/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
@@ -432,8 +432,6 @@ class HexagonGlobalSchedulerImpl : public HexagonPacketizerList {
MachineInstr *MI,
SmallVector<MachineInstr *, HEXAGON_PACKET_SIZE> &Bundle);
- bool CanPromoteToDotNew(MachineInstr *MI, unsigned Reg);
-
bool pullUpPeelBBLoop(MachineBasicBlock *PredBB, MachineBasicBlock *LoopBB);
MachineInstr *findBundleAndBranch(MachineBasicBlock *BB,
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index e6fd858ccb5a8d..7754027f502583 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -107,9 +107,6 @@ class HexagonTargetLowering : public TargetLowering {
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
@@ -121,7 +118,6 @@ class HexagonTargetLowering : public TargetLowering {
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
SDValue
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
index 33edcce995e1d3..e5baaa061a54ca 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
@@ -145,7 +145,6 @@ class HexagonPacketizerList : public VLIWPacketizerList {
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
bool restrictingDepExistInPacket(MachineInstr&, unsigned);
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
- bool isCurifiable(MachineInstr &MI);
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
bool isPromotedToDotNew() const {
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
index 8beee8d7ec8eb6..b4f561ead9d32f 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
@@ -89,7 +89,6 @@ class HexagonMCChecker {
HexagonMCInstrInfo::PredicateInfo Predicated);
// Checks performed.
- bool checkBranches();
bool checkPredicates();
bool checkNewValues();
bool checkRegisters();
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
index 6110c7a93982ca..640090adc571c0 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
@@ -65,7 +65,6 @@ extern cl::opt<bool> HexagonDisableDuplex;
extern const InstrStage HexagonStages[];
MCInstrInfo *createHexagonMCInstrInfo();
-MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
namespace Hexagon_MC {
StringRef selectHexagonCPU(StringRef CPU);
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
index 838672d34741d6..898d75f6410039 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
@@ -172,7 +172,6 @@ class HexagonShuffler {
const bool DoShuffle);
void restrictSlot1AOK(HexagonPacketSummary const &Summary);
void restrictNoSlot1Store(HexagonPacketSummary const &Summary);
- void restrictNoSlot1();
bool restrictStoreLoadOrder(HexagonPacketSummary const &Summary);
void restrictBranchOrder(HexagonPacketSummary const &Summary);
void restrictPreferSlot3(HexagonPacketSummary const &Summary,
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 2104e76fccc5c8..21113e4ee7c3d3 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -204,7 +204,6 @@ class MipsAsmParser : public MCTargetAsmParser {
const AsmToken &Token, SMLoc S);
ParseStatus matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
ParseStatus parseAnyRegister(OperandVector &Operands);
- ParseStatus parseImm(OperandVector &Operands);
ParseStatus parseJumpTarget(OperandVector &Operands);
ParseStatus parseInvNum(OperandVector &Operands);
ParseStatus parseRegisterList(OperandVector &Operands);
@@ -442,11 +441,6 @@ class MipsAsmParser : public MCTargetAsmParser {
bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
- // Helper function that checks if the value of a vector index is within the
- // boundaries of accepted values for each RegisterKind
- // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
- bool validateMSAIndex(int Val, int RegKind);
-
// Selects a new architecture by updating the FeatureBits with the necessary
// info including implied dependencies.
// Internally, it clears all the feature bits related to *any* architecture
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
index 497b3e64df533b..d1503d492ef0fc 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
@@ -181,10 +181,6 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
-
template <unsigned ShiftAmount = 0>
unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
index ec6e74568c5616..1045d387fe0d1c 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
@@ -43,8 +43,6 @@ class Mips16DAGToDAGISel : public MipsDAGToDAGISel {
// Insert instructions to initialize the global base register in the
// first MBB of the function.
void initGlobalBaseReg(MachineFunction &MF);
-
- void initMips16SPAliasReg(MachineFunction &MF);
};
class Mips16DAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy {
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h
index ae77c305f9703b..3ba333095e801a 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.h
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h
@@ -42,8 +42,6 @@ class TargetMachine;
class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
MipsTargetStreamer &getTargetStreamer() const;
- void EmitInstrWithMacroNoAT(const MachineInstr *MI);
-
//===------------------------------------------------------------------===//
// XRay implementation
//===------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index e352cf5492b3bd..75604cc20aaf41 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -526,7 +526,6 @@ using TargetRegisterClass = MCRegisterClass;
MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
MachineBasicBlock *BB,
unsigned Size) const;
- MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
bool isFPCmp, unsigned Opc) const;
MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
index 4122de7646f369..f65998dce3d9b2 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
@@ -34,10 +34,6 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
- std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
- const SDLoc &dl, EVT Ty, bool HasLo,
- bool HasHi);
-
void selectAddE(SDNode *Node, const SDLoc &DL) const;
bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.h b/llvm/lib/Target/Mips/MipsSEISelLowering.h
index 56b26b39f634dc..b4620aa7549171 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.h
@@ -93,8 +93,6 @@ using TargetRegisterClass = MCRegisterClass;
/// depending on the indices in the shuffle.
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFP16_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 58011de3dbd8ab..b83eee4a9c2107 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -133,9 +133,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
// FixR5900 - Enable R5900 short loop erratum fix.
bool FixR5900;
- // isLinux - Target system is Linux. Is false we consider ELFOS for now.
- bool IsLinux;
-
// UseSmallSection - Small section is used.
bool UseSmallSection;
@@ -230,10 +227,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
/// The overridden stack alignment.
MaybeAlign StackAlignOverride;
- // We can override the determination of whether we are in mips16 mode
- // as from the command line
- enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
-
const MipsTargetMachine &TM;
Triple TargetTriple;
@@ -413,10 +406,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
return hasMips32r6() && !StrictAlign;
}
- // Set helper classes
- void setHelperClassesMips16();
- void setHelperClassesMipsSE();
-
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h
index 6897baaede9c4b..6a58b55acd29d4 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.h
+++ b/llvm/lib/Target/NVPTX/NVPTX.h
@@ -84,7 +84,6 @@ void initializeNVPTXProxyRegErasureLegacyPassPass(PassRegistry &);
void initializeNVPTXForwardParamsLegacyPassPass(PassRegistry &);
void initializeNVPTXAddressFolderLegacyPassPass(PassRegistry &);
void initializeNVVMIntrRangePass(PassRegistry &);
-void initializeNVVMReflectPass(PassRegistry &);
void initializeNVPTXAAWrapperPassPass(PassRegistry &);
void initializeNVPTXExternalAAWrapperPass(PassRegistry &);
void initializeNVPTXPeepholeLegacyPassPass(PassRegistry &);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 7411aa11824ff7..186bfa185e135a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -117,7 +117,6 @@ class NVPTXDAGToDAGISel : public SelectionDAGISel {
void Select(SDNode *N) override;
bool tryIntrinsicChain(SDNode *N);
bool tryIntrinsicVoid(SDNode *N);
- void SelectTexSurfHandle(SDNode *N);
bool tryLoad(SDNode *N);
bool tryLoadVector(SDNode *N);
bool tryLDU(SDNode *N);
@@ -127,15 +126,12 @@ class NVPTXDAGToDAGISel : public SelectionDAGISel {
bool tryFence(SDNode *N);
bool tryBFE(SDNode *N);
bool tryBF16ArithToFMA(SDNode *N);
- bool tryConstantFP(SDNode *N);
bool SelectSETP_F16X2(SDNode *N);
bool SelectSETP_BF16X2(SDNode *N);
bool tryUNPACK_VECTOR(SDNode *N);
bool tryEXTRACT_VECTOR_ELEMENT(SDNode *N);
void SelectV2I64toI128(SDNode *N);
void SelectI128toV2I64(SDNode *N);
- void SelectCpAsyncBulkTensorReduceCommon(SDNode *N, unsigned RedOp,
- bool IsIm2Col = false);
void SelectTcgen05Ld(SDNode *N, bool hasOffset = false);
void SelectTcgen05St(SDNode *N, bool hasOffset = false);
void selectAtomicSwap128(SDNode *N);
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
index db37fbf3950962..3b28d5b4f93c1c 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
@@ -62,9 +62,6 @@ MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
/// Construct an PPC ELF object writer.
std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
uint8_t OSABI);
-/// Construct a PPC Mach-O object writer.
-std::unique_ptr<MCObjectTargetWriter>
-createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
/// Construct a PPC XCOFF object writer.
std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit);
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index bd04ebb71b8f05..b50b8fe7b6812c 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -49,7 +49,6 @@ class ModulePass;
FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOptLevel OL);
FunctionPass *createPPCTLSDynamicCallPass();
FunctionPass *createPPCBoolRetToIntPass();
- FunctionPass *createPPCExpandISELPass();
FunctionPass *createPPCPreEmitPeepholePass();
FunctionPass *createPPCExpandAtomicPseudoPass();
FunctionPass *createPPCCTRLoopsPass();
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index f01f7dcc6ab1d7..6d99fef8b568b2 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -438,15 +438,6 @@ class SystemZTargetLowering : public TargetLowering {
SDValue unwrapAddress(SDValue N) const override;
- // If the last instruction before MBBI in MBB was some form of COMPARE,
- // try to replace it with a COMPARE AND BRANCH just before MBBI.
- // CCMask and Target are the BRC-like operands for the branch.
- // Return true if the change was made.
- bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned CCMask,
- MachineBasicBlock *Target) const;
-
// Implement EmitInstrWithCustomInserter for individual operation types.
MachineBasicBlock *emitAdjCallStack(MachineInstr &MI,
MachineBasicBlock *BB) const;
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index cc58efcd7b0057..9fb0561507f934 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -67,8 +67,6 @@ class VEAsmParser : public MCTargetAsmParser {
// Custom parse functions for VE specific operands.
ParseStatus parseMEMOperand(OperandVector &Operands);
ParseStatus parseMEMAsOperand(OperandVector &Operands);
- ParseStatus parseCCOpOperand(OperandVector &Operands);
- ParseStatus parseRDOpOperand(OperandVector &Operands);
ParseStatus parseMImmOperand(OperandVector &Operands);
ParseStatus parseOperand(OperandVector &Operands, StringRef Name);
ParseStatus parseVEAsmOperand(std::unique_ptr<VEOperand> &Operand);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
index 7f2058910cf416..ba5dd448def0f4 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
@@ -49,8 +49,6 @@ class WebAssemblyOptimizeReturnedLegacy final : public FunctionPass {
public:
static char ID;
WebAssemblyOptimizeReturnedLegacy() : FunctionPass(ID) {}
-
- void visitCallBase(CallBase &CB);
};
} // End anonymous namespace
diff --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
index c8b0dbf5972230..a72cb26ac3e0b9 100644
--- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp
+++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
@@ -62,8 +62,6 @@ class X86FixupInstTuningLegacy : public MachineFunctionPass {
StringRef getPassName() const override { return "X86 Fixup Inst Tuning"; }
bool runOnMachineFunction(MachineFunction &MF) override;
- bool processInstruction(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I);
// This pass runs after regalloc and doesn't support VReg operands.
MachineFunctionProperties getRequiredProperties() const override {
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h
index c41c18fe2c07a3..a965fe93f093b1 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.h
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.h
@@ -92,7 +92,6 @@ namespace llvm {
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
- SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
SelectionDAG &DAG) const;
SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL,
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