[llvm] [RISCV][MC] Allow x0 as the destination of qc.inw (PR #225602)

[Zeyi Xu via llvm-commits]

https://github.com/zeyi2 created https://github.com/llvm/llvm-project/pull/225602

None

>From 90652c97585d776cc61db7a6ab931523f308e557 Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Wed, 23 Sep 2026 14:02:39 +0800
Subject: [PATCH] [RISCV][MC] Allow x0 as the destination of qc.inw

---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 +-
 llvm/test/MC/RISCV/xqciio-invalid.s         | 4 ----
 llvm/test/MC/RISCV/xqciio-valid.s           | 4 ++++
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 643d04d1da878e..3dd4edd0530b1c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1132,7 +1132,7 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
     let imm12 = imm14{13-2};
   }
 
-  def QC_INW : RVInstI<0b101, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
+  def QC_INW : RVInstI<0b101, OPC_CUSTOM_0, (outs GPR:$rd),
                        (ins GPR:$rs1, uimm14lsb00_optional:$imm14),
                        "qc.inw", "$rd, ${imm14}(${rs1})"> {
     bits<14> imm14;
diff --git a/llvm/test/MC/RISCV/xqciio-invalid.s b/llvm/test/MC/RISCV/xqciio-invalid.s
index 3a4c852c50f92b..08fa01645fd79e 100644
--- a/llvm/test/MC/RISCV/xqciio-invalid.s
+++ b/llvm/test/MC/RISCV/xqciio-invalid.s
@@ -25,10 +25,6 @@ qc.inw x23, 16380(17)
 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciio' (Qualcomm uC External Input Output Extension)
 qc.inw x23, x17
 
-# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
-qc.inw x0, 16380(x17)
-
 # CHECK-PLUS: :[[@LINE+2]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
 # CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
 qc.inw x23, 16384(x17)
diff --git a/llvm/test/MC/RISCV/xqciio-valid.s b/llvm/test/MC/RISCV/xqciio-valid.s
index 3d6ecf2560a87b..750ad536af9c50 100644
--- a/llvm/test/MC/RISCV/xqciio-valid.s
+++ b/llvm/test/MC/RISCV/xqciio-valid.s
@@ -18,3 +18,7 @@ qc.outw x5, 2048(x10)
 # CHECK-INST: qc.inw    s7, 16380(a7)
 # CHECK-ENC: encoding: [0x8b,0xdb,0xf8,0xff]
 qc.inw x23, 16380(x17)
+
+# CHECK-INST: qc.inw    zero, 16380(a7)
+# CHECK-ENC: encoding: [0x0b,0xd0,0xf8,0xff]
+qc.inw x0, 16380(x17)