[llvm] [NFC][AMDGPU] Pre-commit test that exposes subreg copies into PHI nodes (PR #222152)

[Zach Goldthorpe via llvm-commits]

https://github.com/zGoldthorpe updated https://github.com/llvm/llvm-project/pull/222152

>From 442640a8f654b0476a541e5dd4ad31c65010bb6b Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Tue, 8 Sep 2026 15:44:20 -0500
Subject: [PATCH 1/2] [NFC][AMDGPU] Pre-commit test that exposes subreg copies
 into PHI nodes

---
 .../AMDGPU/fix-sgpr-copies-f16-true16.mir     | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
index 6c96be0860b432..84209fb1a96143 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
@@ -256,6 +256,74 @@ body:             |
     S_ENDPGM 0, implicit %3
 ...
 
+---
+name:            copy_lo16_sreg32_usedby_phi32
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: copy_lo16_sreg32_usedby_phi32
+  ; GCN: bb.0:
+  ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; GCN-NEXT:   liveins: $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF1]]
+  ; GCN-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.1:
+  ; GCN-NEXT:   successors: %bb.2(0x80000000)
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.2:
+  ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[DEF]].lo16, %bb.1
+  ; GCN-NEXT:   S_ENDPGM 0, implicit [[PHI]]
+  bb.0:
+    liveins: $scc
+    %0:vgpr_32 = IMPLICIT_DEF
+    %1:sreg_32 = IMPLICIT_DEF
+    S_CBRANCH_SCC1 %bb.2, implicit $scc
+
+  bb.1:
+    %2:sreg_32 = COPY %0.lo16
+
+  bb.2:
+    %3:sreg_32 = PHI %1, %bb.0, %2, %bb.1
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name:            copy_hi16_sreg32_usedby_phi32
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: copy_hi16_sreg32_usedby_phi32
+  ; GCN: bb.0:
+  ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; GCN-NEXT:   liveins: $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF1]]
+  ; GCN-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.1:
+  ; GCN-NEXT:   successors: %bb.2(0x80000000)
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.2:
+  ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[DEF]].hi16, %bb.1
+  ; GCN-NEXT:   S_ENDPGM 0, implicit [[PHI]]
+  bb.0:
+    liveins: $scc
+    %0:vgpr_32 = IMPLICIT_DEF
+    %1:sreg_32 = IMPLICIT_DEF
+    S_CBRANCH_SCC1 %bb.2, implicit $scc
+
+  bb.1:
+    %2:sreg_32 = COPY %0.hi16
+
+  bb.2:
+    %3:sreg_32 = PHI %1, %bb.0, %2, %bb.1
+    S_ENDPGM 0, implicit %3
+...
+
 ---
 name:            S_FMAC_F16
 body:             |

>From bb397eacdd7e57a7fc5498f68180bef72483a9f2 Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Tue, 22 Sep 2026 15:59:53 -0500
Subject: [PATCH 2/2] Add reviewer test case

---
 .../AMDGPU/fix-sgpr-copies-f16-true16.mir     | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
index 84209fb1a96143..fac10a08d808b5 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
@@ -324,6 +324,46 @@ body:             |
     S_ENDPGM 0, implicit %3
 ...
 
+---
+name:            salu16_sreg32_usedby_phi32
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: salu16_sreg32_usedby_phi32
+  ; GCN: bb.0:
+  ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; GCN-NEXT:   liveins: $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]], %subreg.lo16, [[DEF1]], %subreg.hi16
+  ; GCN-NEXT:   [[V_TRUNC_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_TRUNC_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_TRUNC_F16_t16_e64_]], implicit $exec
+  ; GCN-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.1:
+  ; GCN-NEXT:   successors: %bb.2(0x80000000)
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.2:
+  ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
+  ; GCN-NEXT:   S_ENDPGM 0, implicit [[PHI]]
+  bb.0:
+    liveins: $scc
+    %0:vgpr_16 = IMPLICIT_DEF
+    %1:sreg_32 = COPY %0
+    %2:sreg_32 = S_TRUNC_F16 %1, implicit $mode
+    S_CBRANCH_SCC1 %bb.2, implicit $scc
+
+  bb.1:
+    %3:sreg_32 = IMPLICIT_DEF
+
+  bb.2:
+    %4:sreg_32 = PHI %2, %bb.0, %3, %bb.1
+    S_ENDPGM 0, implicit %4
+...
+
 ---
 name:            S_FMAC_F16
 body:             |