[llvm] cdaed31 - [AMDGPU][NFC] Auto-generate llvm.amdgcn.wqm.vote test checks (#224772)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 12:48:47 PDT 2026
Author: vangthao95
Date: 2026-09-22T12:48:40-07:00
New Revision: cdaed31318e9d49fcfa47d7229c18168611f062f
URL: https://github.com/llvm/llvm-project/commit/cdaed31318e9d49fcfa47d7229c18168611f062f
DIFF: https://github.com/llvm/llvm-project/commit/cdaed31318e9d49fcfa47d7229c18168611f062f.diff
LOG: [AMDGPU][NFC] Auto-generate llvm.amdgcn.wqm.vote test checks (#224772)
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
index 6bca92ded6073..4f5b2d2f47151 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
@@ -1,16 +1,33 @@
-; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s
-; xUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s
-; RUN: llc -global-isel=0 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
-; xUN: llc -global-isel=1 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
-; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
-; xUN: llc -global-isel=1 -mtriple=amdgpu11.00 < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX8 %s
+; xUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10 %s
+; xUN: llc -global-isel=1 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 < %s | FileCheck -check-prefixes=GFX11 %s
+; xUN: llc -global-isel=1 -mtriple=amdgpu11.00 < %s | FileCheck -check-prefixes=GFX11 %s
-;CHECK-LABEL: {{^}}ret:
-;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1
-;WAVE64: s_wqm_b64 [[WQM:[^,]+]], [[CMP]]
-;WAVE32: s_wqm_b32 [[WQM:[^,]+]], [[CMP]]
-;CHECK: v_cndmask_b32_e64 v0, 0, 1.0, [[WQM]]
define amdgpu_ps float @ret(i32 %v0, i32 %v1) #1 {
+; GFX8-LABEL: ret:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX8-NEXT: s_wqm_b64 s[0:1], vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: ret:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: s_wqm_b32 s0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: ret:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: s_wqm_b32 s0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%c = icmp eq i32 %v0, %v1
%w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
@@ -18,20 +35,50 @@ main_body:
ret float %r
}
-;CHECK-LABEL: {{^}}true:
-;WAVE64: s_wqm_b64
-;WAVE32: s_wqm_b32
define amdgpu_ps float @true() #1 {
+; GFX8-LABEL: true:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_wqm_b64 s[0:1], -1
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: true:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_wqm_b32 s0, -1
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: true:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_wqm_b32 s0, -1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%w = call i1 @llvm.amdgcn.wqm.vote(i1 true)
%r = select i1 %w, float 1.0, float 0.0
ret float %r
}
-;CHECK-LABEL: {{^}}false:
-;WAVE64: s_wqm_b64
-;WAVE32: s_wqm_b32
define amdgpu_ps float @false() #1 {
+; GFX8-LABEL: false:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: s_wqm_b64 s[0:1], 0
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: false:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_wqm_b32 s0, 0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: false:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_wqm_b32 s0, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%w = call i1 @llvm.amdgcn.wqm.vote(i1 false)
%r = select i1 %w, float 1.0, float 0.0
@@ -39,21 +86,61 @@ main_body:
}
; Note: an almost identical test for this exists in llvm.amdgcn.kill.ll
-;CHECK-LABEL: {{^}}kill:
-;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1
-
-;WAVE64: s_wqm_b64 [[WQM:[^,]+]], [[CMP]]
-;WAVE64: s_andn2_b64 [[KILL:[^,]+]], exec, [[WQM]]
-;WAVE64: s_andn2_b64 [[MASK:[^,]+]], [[EXEC:[^,]+]], [[KILL]]
-;WAVE64: s_and_b64 exec, exec, [[MASK]]
-
-;WAVE32: s_wqm_b32 [[WQM:[^,]+]], [[CMP]]
-;WAVE32: s_and{{n2|_not1}}_b32 [[KILL:[^,]+]], exec_lo, [[WQM]]
-;WAVE32: s_and{{n2|_not1}}_b32 [[MASK:[^,]+]], [[EXEC:[^,]+]], [[KILL]]
-;WAVE32: s_and_b32 exec_lo, exec_lo, [[MASK]]
-
-;CHECK: s_endpgm
define amdgpu_ps float @kill(i32 %v0, i32 %v1) #1 {
+; GFX8-LABEL: kill:
+; GFX8: ; %bb.0: ; %main_body
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
+; GFX8-NEXT: s_wqm_b64 s[2:3], vcc
+; GFX8-NEXT: s_mov_b64 s[0:1], exec
+; GFX8-NEXT: s_andn2_b64 s[2:3], exec, s[2:3]
+; GFX8-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]
+; GFX8-NEXT: s_cbranch_scc0 .LBB3_2
+; GFX8-NEXT: ; %bb.1: ; %main_body
+; GFX8-NEXT: s_and_b64 exec, exec, s[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, 0
+; GFX8-NEXT: s_branch .LBB3_3
+; GFX8-NEXT: .LBB3_2:
+; GFX8-NEXT: s_mov_b64 exec, 0
+; GFX8-NEXT: exp null, off, off, off, off done vm
+; GFX8-NEXT: s_endpgm
+; GFX8-NEXT: .LBB3_3:
+;
+; GFX10-LABEL: kill:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX10-NEXT: s_mov_b32 s0, exec_lo
+; GFX10-NEXT: s_wqm_b32 s1, vcc_lo
+; GFX10-NEXT: s_andn2_b32 s1, exec_lo, s1
+; GFX10-NEXT: s_andn2_b32 s0, s0, s1
+; GFX10-NEXT: s_cbranch_scc0 .LBB3_2
+; GFX10-NEXT: ; %bb.1: ; %main_body
+; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: s_branch .LBB3_3
+; GFX10-NEXT: .LBB3_2:
+; GFX10-NEXT: s_mov_b32 exec_lo, 0
+; GFX10-NEXT: exp null, off, off, off, off done vm
+; GFX10-NEXT: s_endpgm
+; GFX10-NEXT: .LBB3_3:
+;
+; GFX11-LABEL: kill:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
+; GFX11-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-NEXT: s_wqm_b32 s1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_not1_b32 s1, exec_lo, s1
+; GFX11-NEXT: s_and_not1_b32 s0, s0, s1
+; GFX11-NEXT: s_cbranch_scc0 .LBB3_2
+; GFX11-NEXT: ; %bb.1: ; %main_body
+; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_branch .LBB3_3
+; GFX11-NEXT: .LBB3_2:
+; GFX11-NEXT: s_mov_b32 exec_lo, 0
+; GFX11-NEXT: exp mrt0, off, off, off, off done
+; GFX11-NEXT: s_endpgm
+; GFX11-NEXT: .LBB3_3:
main_body:
%c = icmp eq i32 %v0, %v1
%w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
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