[llvm] [AArch64] Enable quad variant st1b/ld1b for callee-saved spills (PR #225100)
Kieran B via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 07:41:33 PDT 2026
================
@@ -1806,37 +1822,57 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
bool PairFitsImmRange =
PairOffset / Scale >= -64 && PairOffset / Scale <= 63;
switch (RPI.Type) {
- case RegPairInfo::GPR:
+ case RegGroupInfo::GPR:
if (AArch64::GPR64RegClass.contains(NextReg) && PairFitsImmRange &&
!invalidateRegisterPairing(SpillExtendedVolatile, SpillCount,
RPI.Reg1, NextReg, IsWindows,
NeedsWinCFI, NeedsFrameRecord, TRI))
RPI.Reg2 = NextReg;
break;
- case RegPairInfo::FPR64:
+ case RegGroupInfo::FPR64:
if (AArch64::FPR64RegClass.contains(NextReg) && PairFitsImmRange &&
!invalidateRegisterPairing(SpillExtendedVolatile, SpillCount,
RPI.Reg1, NextReg, IsWindows,
NeedsWinCFI, NeedsFrameRecord, TRI))
RPI.Reg2 = NextReg;
break;
- case RegPairInfo::FPR128:
+ case RegGroupInfo::FPR128:
if (AArch64::FPR128RegClass.contains(NextReg) && PairFitsImmRange)
RPI.Reg2 = NextReg;
break;
- case RegPairInfo::PPR:
+ case RegGroupInfo::PPR:
break;
- case RegPairInfo::ZPR:
- if (!NeedsWinCFI && AFI->getPredicateRegForFillSpill() != 0 &&
- ((RPI.Reg1 - AArch64::Z0) & 1) == 0 && (NextReg == RPI.Reg1 + 1)) {
- // Calculate offset of register pair to see if pair instruction can be
- // used.
- int Offset = (ScalableByteOffset + StackFillDir * 2 * Scale) / Scale;
- if ((-16 <= Offset && Offset <= 14) && (Offset % 2 == 0))
- RPI.Reg2 = NextReg;
+ case RegGroupInfo::ZPR:
+ if (!NeedsWinCFI && AFI->getPredicateRegForFillSpill() != 0) {
----------------
kieroxide wrote:
Done
https://github.com/llvm/llvm-project/pull/225100
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