[llvm] [AArch64] Enable quad variant st1b/ld1b for callee-saved spills (PR #225100)

[Kieran B via llvm-commits]

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@@ -1759,32 +1775,32 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
 
   // When iterating backwards, the loop condition relies on unsigned wraparound.
   for (unsigned i = FirstReg; i < Count; i += RegInc) {
-    RegPairInfo RPI;
+    RegGroupInfo RPI;
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kieroxide wrote:

I have renamed all instances of RPI

https://github.com/llvm/llvm-project/pull/225100