[llvm] SelectionDAG: Don't pad the source of ADDRSPACECAST if it's legal. (PR #225390)

[via llvm-commits]

https://github.com/sujianIBM updated https://github.com/llvm/llvm-project/pull/225390

>From daea9f84eeab62ce29482eb31c34594ec42c6a72 Mon Sep 17 00:00:00 2001
From: Jian Su <jian.su at ibm.com>
Date: Tue, 22 Sep 2026 12:35:16 +0000
Subject: [PATCH 1/2] Don't pad the source of ADDRSPACECAST if it's legal.

---
 llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 48fc990700b3c..624fa69a6e023 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -6333,12 +6333,13 @@ SDValue DAGTypeLegalizer::WidenVecRes_ADDRSPACECAST(SDNode *N) {
 
   // The source has the same number of elements as the result, so widen it to
   // match WidenVT. It only lives in the widened-vector map if it is itself
-  // widened; otherwise pad it up to the widened element count.
+  // widened; otherwise pad it up to the widened element count
+  // when it is illegal.
   SDValue InOp = N->getOperand(0);
   EVT InVT = InOp.getValueType();
   if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
     InOp = GetWidenedVector(InOp);
-  } else {
+  } else if (getTypeAction(InVT) != TargetLowering::TypeLegal) {
     EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(),
                                      InVT.getVectorElementType(), WidenEC);
     InOp = DAG.getInsertSubvector(DL, DAG.getPOISON(InWidenVT), InOp, 0);

>From 3132c8185346688eacd2d770177cb2bd6b7544f6 Mon Sep 17 00:00:00 2001
From: Jian Su <jian.su at ibm.com>
Date: Tue, 22 Sep 2026 14:24:08 +0000
Subject: [PATCH 2/2] Add test.

---
 .../SelectionDAG/LegalizeVectorTypes.cpp      |  5 +--
 llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll  | 33 +++++++++++++++++++
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 624fa69a6e023..b13a40e982977 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -6337,9 +6337,10 @@ SDValue DAGTypeLegalizer::WidenVecRes_ADDRSPACECAST(SDNode *N) {
   // when it is illegal.
   SDValue InOp = N->getOperand(0);
   EVT InVT = InOp.getValueType();
-  if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
+  TargetLowering::LegalizeTypeAction InAction = getTypeAction(InVT);
+  if (InAction == TargetLowering::TypeWidenVector) {
     InOp = GetWidenedVector(InOp);
-  } else if (getTypeAction(InVT) != TargetLowering::TypeLegal) {
+  } else if (InAction != TargetLowering::TypeLegal) {
     EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(),
                                      InVT.getVectorElementType(), WidenEC);
     InOp = DAG.getInsertSubvector(DL, DAG.getPOISON(InWidenVT), InOp, 0);
diff --git a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
index cae54638c3191..ad079e2e8689f 100644
--- a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
@@ -376,3 +376,36 @@ declare ptr @__malloc31(i64)
 declare signext i32 @foo(...)
 
 declare ptr addrspace(1) @domalloc(i64)
+
+define void @f1(ptr %inp, ptr %outp) "target-features"="-vector" {
+; CHECK-LABEL: f1 DS 0H
+; CHECK:        iilf 0,2147483647
+; CHECK-NEXT:   iilf 3,2147483647
+; CHECK-NEXT:   n 0,12(1)
+; CHECK-NEXT:   n 3,4(1)
+; CHECK-NEXT:   st 0,4(2)
+; CHECK-NEXT:   st 3,0(2)
+; CHECK-NEXT:   b 2(7)
+  %in = load <2 x ptr>, ptr %inp, align 8
+  %out = addrspacecast <2 x ptr> %in to <2 x ptr addrspace(1)>
+  store <2 x ptr addrspace(1)> %out, ptr %outp, align 4
+  ret void
+}
+
+define void @f1_v(ptr %inp, ptr %outp) "target-features"="+vector" {
+; CHECK-LABEL: f1_v DS 0H
+; CHECK:        vl 0,0(1),3
+; CHECK-NEXT:   vlgvg 0,0,1
+; CHECK-NEXT:   llgtr 0,0
+; CHECK-NEXT:   lghi 1,0
+; CHECK-NEXT:   vlvgp 1,0,1
+; CHECK-NEXT:   vlgvg 0,0,0
+; CHECK-NEXT:   nilh 0,32767
+; CHECK-NEXT:   vlvgf 1,0,0
+; CHECK-NEXT:   vsteg 1,0(2),0
+; CHECK-NEXT:   b 2(7)
+  %in = load <2 x ptr>, ptr %inp, align 8
+  %out = addrspacecast <2 x ptr> %in to <2 x ptr addrspace(1)>
+  store <2 x ptr addrspace(1)> %out, ptr %outp, align 4
+  ret void
+}