[llvm] [AMDGPU] Refactor isDPALU_DPP to only check if the instruction requires the feature (PR #224373)

[Domenic Nutile via llvm-commits]

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@@ -5151,6 +5151,7 @@ bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
     unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();
 
     if (!AMDGPU::isLegalDPALU_DPPControl(getSTI(), DppCtrl) &&
+        getSTI().hasFeature(AMDGPU::FeatureDPALU_DPP) &&
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saxlungs wrote:

In this spot, I believe this check is correct to add. The error text is specifically checking that for the current DP ALU DPP-supporting asic that we're using a version of the DPP that's valid for that asic, i.e. make sure `row_share` is only on GFX12. So I don't think this error message is relevant if you aren't on an asic that support DP ALU DPP at all. As-is without any changes we don't go into this block on other targets anyway because isDPALU_DP returns false.

GCNDPPCombine.cpp has two different checks for each failure mode. I think we could add those checks here and in AMDGPUInstPrinter.cpp to handle the case where we're on an asic that doesn't support DP ALU DPP at all, but I think that should be a follow up if desired.

https://github.com/llvm/llvm-project/pull/224373