[llvm] [AMDGPU] Pre-commit tests for FLAT_SCRATCH const offset promotion (NFC) (PR #225397)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 06:33:26 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Arseniy Obolenskiy (aobolensk)
<details>
<summary>Changes</summary>
Prerequisite for https://github.com/llvm/llvm-project/pull/212507
---
Patch is 73.45 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225397.diff
2 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (+1197-10)
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir (+25-2)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
index b113380874cd3..a1e4f704e871c 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -5,8 +5,11 @@
; RUN: llc -mtriple=amdgpu9.0a < %s | FileCheck -check-prefixes=GFX9,GFX90A %s
; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgpu9.00 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=GFX9-FLATSCR %s
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=GFX10-FLATSCR %s
declare i64 @_Z13get_global_idj(i32) #0
+declare i32 @llvm.amdgcn.workitem.id.x()
define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX8-LABEL: clmem_read_simplified:
@@ -309,6 +312,140 @@ define amdgpu_kernel void @clmem_read_simplified(ptr addrspace(1) %buffer) {
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
; GFX11-NEXT: global_store_b64 v16, v[0:1], s[34:35]
; GFX11-NEXT: s_endpgm
+;
+; GFX9-FLATSCR-LABEL: clmem_read_simplified:
+; GFX9-FLATSCR: ; %bb.0: ; %entry
+; GFX9-FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
+; GFX9-FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
+; GFX9-FLATSCR-NEXT: s_getpc_b64 s[0:1]
+; GFX9-FLATSCR-NEXT: s_add_u32 s0, s0, _Z13get_global_idj at gotpcrel32@lo+4
+; GFX9-FLATSCR-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
+; GFX9-FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX9-FLATSCR-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v31, v0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-FLATSCR-NEXT: s_mov_b32 s32, 0
+; GFX9-FLATSCR-NEXT: ; implicit-def: $sgpr15
+; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-FLATSCR-NEXT: s_swappc_b64 s[30:31], s[2:3]
+; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 7, v0
+; GFX9-FLATSCR-NEXT: v_and_b32_e32 v18, 0xffff8000, v1
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, s35
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, s34, v18
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, 3
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: s_movk_i32 s1, 0x2000
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[2:3], v[0:1], off
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:2048
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v6, vcc, s1, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[8:9], v[6:7], off offset:-4096
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x1000
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v10, vcc, s0, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[12:13], v[10:11], off offset:2048
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[14:15], v[6:7], off
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[16:17], v[6:7], off offset:2048
+; GFX9-FLATSCR-NEXT: s_movk_i32 s0, 0x3000
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[6:7], v[0:1], off
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(6)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v4, v2
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(5)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(4)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v12, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v13, v1, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(3)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v14, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v15, v1, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(2)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v16, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v17, v1, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v6, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v1, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc
+; GFX9-FLATSCR-NEXT: global_store_dwordx2 v18, v[0:1], s[34:35]
+; GFX9-FLATSCR-NEXT: s_endpgm
+;
+; GFX10-FLATSCR-LABEL: clmem_read_simplified:
+; GFX10-FLATSCR: ; %bb.0: ; %entry
+; GFX10-FLATSCR-NEXT: s_add_u32 s8, s8, s13
+; GFX10-FLATSCR-NEXT: s_mov_b32 s32, 0
+; GFX10-FLATSCR-NEXT: s_addc_u32 s9, s9, 0
+; GFX10-FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s8
+; GFX10-FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s9
+; GFX10-FLATSCR-NEXT: s_getpc_b64 s[0:1]
+; GFX10-FLATSCR-NEXT: s_add_u32 s0, s0, _Z13get_global_idj at gotpcrel32@lo+4
+; GFX10-FLATSCR-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v0
+; GFX10-FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX10-FLATSCR-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-FLATSCR-NEXT: ; implicit-def: $sgpr15
+; GFX10-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-FLATSCR-NEXT: s_swappc_b64 s[30:31], s[2:3]
+; GFX10-FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 7, v0
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v2, 3
+; GFX10-FLATSCR-NEXT: v_and_b32_e32 v20, 0xffff8000, v1
+; GFX10-FLATSCR-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v1, s0, s34, v20
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v2, s0, s35, 0, s0
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x1000
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v8, vcc_lo, v0, 0x2000
+; GFX10-FLATSCR-NEXT: s_clause 0x1
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[4:5], v[0:1], off
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_clause 0x1
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[10:11], v[2:3], off
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[12:13], v[8:9], off offset:-2048
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, vcc_lo, v0, 0x3000
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_clause 0x1
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[14:15], v[8:9], off
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[16:17], v[2:3], off offset:-2048
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, 0x3800, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_clause 0x1
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[8:9], v[2:3], off
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[18:19], v[0:1], off
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(6)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v6, v4
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v5, vcc_lo
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(5)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v10, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(4)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v12, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(3)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v14, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v15, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(2)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v16, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v17, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(1)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v8, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, v18, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v19, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: global_store_dwordx2 v20, v[0:1], s[34:35]
+; GFX10-FLATSCR-NEXT: s_endpgm
entry:
%call = tail call i64 @_Z13get_global_idj(i32 0)
%conv = and i64 %call, 255
@@ -929,6 +1066,220 @@ define hidden amdgpu_kernel void @clmem_read(ptr addrspace(1) %buffer) {
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s35, 0, s0
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_endpgm
+;
+; GFX9-FLATSCR-LABEL: clmem_read:
+; GFX9-FLATSCR: ; %bb.0: ; %entry
+; GFX9-FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
+; GFX9-FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
+; GFX9-FLATSCR-NEXT: s_getpc_b64 s[0:1]
+; GFX9-FLATSCR-NEXT: s_add_u32 s0, s0, _Z13get_global_idj at gotpcrel32@lo+4
+; GFX9-FLATSCR-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
+; GFX9-FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX9-FLATSCR-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v31, v0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-FLATSCR-NEXT: s_mov_b32 s32, 0
+; GFX9-FLATSCR-NEXT: ; implicit-def: $sgpr15
+; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-FLATSCR-NEXT: s_swappc_b64 s[30:31], s[2:3]
+; GFX9-FLATSCR-NEXT: v_and_b32_e32 v1, 0xff, v0
+; GFX9-FLATSCR-NEXT: v_lshlrev_b32_e32 v0, 17, v0
+; GFX9-FLATSCR-NEXT: v_and_b32_e32 v6, 0xfe000000, v0
+; GFX9-FLATSCR-NEXT: v_lshl_or_b32 v0, v1, 3, v6
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, s35
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, 0x2800, v0
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x7f
+; GFX9-FLATSCR-NEXT: s_movk_i32 s2, 0xf000
+; GFX9-FLATSCR-NEXT: s_movk_i32 s3, 0x1000
+; GFX9-FLATSCR-NEXT: s_movk_i32 s4, 0x2000
+; GFX9-FLATSCR-NEXT: .LBB1_1: ; %for.cond.preheader
+; GFX9-FLATSCR-NEXT: ; =>This Loop Header: Depth=1
+; GFX9-FLATSCR-NEXT: ; Child Loop BB1_2 Depth 2
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, v0
+; GFX9-FLATSCR-NEXT: s_mov_b32 s5, 0
+; GFX9-FLATSCR-NEXT: .LBB1_2: ; %for.body
+; GFX9-FLATSCR-NEXT: ; Parent Loop BB1_1 Depth=1
+; GFX9-FLATSCR-NEXT: ; => This Inner Loop Header: Depth=2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v8, vcc, 0xffffe000, v2
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v9, vcc, -1, v3, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[14:15], v[8:9], off offset:-2048
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[10:11], v[2:3], off offset:-4096
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[12:13], v[2:3], off offset:-2048
+; GFX9-FLATSCR-NEXT: s_addk_i32 s5, 0x2000
+; GFX9-FLATSCR-NEXT: s_cmp_gt_u32 s5, 0x3fffff
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(2)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v16, vcc, v14, v4
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v17, vcc, v15, v5, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[14:15], v[8:9], off
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v14, vcc, v14, v16
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v15, vcc, v15, v17, vcc
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v8, vcc, s2, v2
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v9, vcc, -1, v3, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[8:9], v[8:9], off offset:-2048
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v14, vcc, v8, v14
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v15, vcc, v9, v15, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[8:9], v[2:3], off offset:2048
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v14, vcc, v10, v14
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v11, vcc, v11, v15, vcc
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e64 v14, s[0:1], v12, v14
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e64 v15, s[0:1], v13, v11, s[0:1]
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v10, vcc, s3, v2
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e64 v12, s[0:1], s4, v2
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e64 v13, vcc, 0, v3, s[0:1]
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v16, vcc, v4, v14
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v17, vcc, v5, v15, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[4:5], v[12:13], off offset:-4096
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[14:15], v[10:11], off offset:2048
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(2)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v16, vcc, v8, v16
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v17, vcc, v9, v17, vcc
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[8:9], v[12:13], off
+; GFX9-FLATSCR-NEXT: global_load_dwordx2 v[10:11], v[12:13], off offset:2048
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, 0x10000, v2
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(3)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v4, vcc, v4, v16
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v17, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(2)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v4, vcc, v14, v4
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v5, vcc, v15, v5, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(1)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
+; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v4, vcc, v10, v4
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v5, vcc, v11, v5, vcc
+; GFX9-FLATSCR-NEXT: s_cbranch_scc0 .LBB1_2
+; GFX9-FLATSCR-NEXT: ; %bb.3: ; %while.cond.loopexit
+; GFX9-FLATSCR-NEXT: ; in Loop: Header=BB1_1 Depth=1
+; GFX9-FLATSCR-NEXT: v_subrev_co_u32_e32 v7, vcc, 1, v7
+; GFX9-FLATSCR-NEXT: s_and_b64 vcc, exec, vcc
+; GFX9-FLATSCR-NEXT: s_cbranch_vccz .LBB1_1
+; GFX9-FLATSCR-NEXT: ; %bb.4: ; %while.end
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, s35
+; GFX9-FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, s34, v6
+; GFX9-FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-FLATSCR-NEXT: global_store_dwordx2 v[0:1], v[4:5], off
+; GFX9-FLATSCR-NEXT: s_endpgm
+;
+; GFX10-FLATSCR-LABEL: clmem_read:
+; GFX10-FLATSCR: ; %bb.0: ; %entry
+; GFX10-FLATSCR-NEXT: s_add_u32 s8, s8, s13
+; GFX10-FLATSCR-NEXT: s_mov_b32 s32, 0
+; GFX10-FLATSCR-NEXT: s_addc_u32 s9, s9, 0
+; GFX10-FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s8
+; GFX10-FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s9
+; GFX10-FLATSCR-NEXT: s_getpc_b64 s[0:1]
+; GFX10-FLATSCR-NEXT: s_add_u32 s0, s0, _Z13get_global_idj at gotpcrel32@lo+4
+; GFX10-FLATSCR-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj at gotpcrel32@hi+12
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v31, v0
+; GFX10-FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX10-FLATSCR-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-FLATSCR-NEXT: ; implicit-def: $sgpr15
+; GFX10-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-FLATSCR-NEXT: s_swappc_b64 s[30:31], s[2:3]
+; GFX10-FLATSCR-NEXT: v_lshlrev_b32_e32 v1, 17, v0
+; GFX10-FLATSCR-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v7, 0x7f
+; GFX10-FLATSCR-NEXT: v_and_b32_e32 v6, 0xfe000000, v1
+; GFX10-FLATSCR-NEXT: v_lshl_or_b32 v0, v0, 3, v6
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, s0, s34, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v1, s0, s35, 0, s0
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v0, vcc_lo, 0x2800, v0
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
+; GFX10-FLATSCR-NEXT: .LBB1_1: ; %for.cond.preheader
+; GFX10-FLATSCR-NEXT: ; =>This Loop Header: Depth=1
+; GFX10-FLATSCR-NEXT: ; Child Loop BB1_2 Depth 2
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v5, v1
+; GFX10-FLATSCR-NEXT: v_mov_b32_e32 v4, v0
+; GFX10-FLATSCR-NEXT: s_mov_b32 s1, 0
+; GFX10-FLATSCR-NEXT: .LBB1_2: ; %for.body
+; GFX10-FLATSCR-NEXT: ; Parent Loop BB1_1 Depth=1
+; GFX10-FLATSCR-NEXT: ; => This Inner Loop Header: Depth=2
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v8, vcc_lo, v4, 0xffffe000
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, -1, v5, vcc_lo
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v10, vcc_lo, v4, 0xfffff000
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, -1, v5, vcc_lo
+; GFX10-FLATSCR-NEXT: s_clause 0x5
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[12:13], v[8:9], off offset:-2048
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[14:15], v[8:9], off
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[16:17], v[10:11], off offset:-2048
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[18:19], v[10:11], off
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[20:21], v[4:5], off offset:-2048
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[22:23], v[4:5], off
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v8, vcc_lo, v4, 0x1000
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v5, vcc_lo
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v10, vcc_lo, v4, 0x2000
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[24:25], v[8:9], off offset:-2048
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v26, vcc_lo, 0x2800, v4
+; GFX10-FLATSCR-NEXT: s_clause 0x1
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[28:29], v[10:11], off offset:-2048
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[8:9], v[8:9], off
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v27, vcc_lo, 0, v5, vcc_lo
+; GFX10-FLATSCR-NEXT: s_clause 0x1
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[30:31], v[10:11], off
+; GFX10-FLATSCR-NEXT: global_load_dwordx2 v[32:33], v[26:27], off
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v4, vcc_lo, 0x10000, v4
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
+; GFX10-FLATSCR-NEXT: s_addk_i32 s1, 0x2000
+; GFX10-FLATSCR-NEXT: s_cmp_gt_u32 s1, 0x3fffff
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(10)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, s0, v12, v2
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v3, s0, v13, v3, s0
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(9)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, s0, v14, v2
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v3, s0, v15, v3, s0
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(8)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, s0, v16, v2
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v3, s0, v17, v3, s0
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(7)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, s0, v18, v2
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v3, s0, v19, v3, s0
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(6)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, s0, v20, v2
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v3, s0, v21, v3, s0
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(5)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, s0, v22, v2
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v3, s0, v23, v3, s0
+; GFX10-FLATSCR-NEXT: s_waitcnt vmcnt(4)
+; GFX10-FLATSCR-NEXT: v_add_co_u32 v2, s0, v24, v2
+; GFX10-FLATSCR-NEXT: v_add_co_ci_u32_e64 v3, s0, v25, v3, s0
+; GF...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/225397
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