[llvm] [AArch64] Enable quad variant st1b/ld1b for callee-saved spills (PR #225100)

[Benjamin Maxwell via llvm-commits]

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@@ -1685,7 +1701,7 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
                                     MachineFunction &MF,
                                     ArrayRef<CalleeSavedInfo> CSI,
                                     const TargetRegisterInfo *TRI,
-                                    SmallVectorImpl<RegPairInfo> &RegPairs,
+                                    SmallVectorImpl<RegGroupInfo> &RegPairs,
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MacDue wrote:

```suggestion
                                    SmallVectorImpl<RegGroupInfo> &RegGroups,
```

https://github.com/llvm/llvm-project/pull/225100