[llvm] [ARM] Replace uses of ARM::NoRegister with Register() or isValid() NFC (PR #224083)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 04:52:51 PDT 2026
https://github.com/janr-bay updated https://github.com/llvm/llvm-project/pull/224083
>From b9002dbd2bfe74ca00ea45a977420ed084719565 Mon Sep 17 00:00:00 2001
From: Jan Rehders <jrehders at baylibre.com>
Date: Tue, 15 Sep 2026 19:54:20 +0200
Subject: [PATCH 1/3] [ARM] Replace uses of ARM::NoRegister with Register() or
isValid() NFC
---
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 4 ++--
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 ++--
llvm/lib/Target/ARM/ARMBlockPlacement.cpp | 2 +-
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 2 +-
.../ARM/ARMFixCortexA57AES1742098Pass.cpp | 2 +-
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 +-
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 2 +-
.../ARM/MVETPAndVPTOptimisationsPass.cpp | 2 +-
llvm/lib/Target/ARM/MVETailPredUtils.h | 6 ++---
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 23 +++++++++----------
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp | 2 +-
11 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index a9d8f1e749fed..bb8c99d591a35 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1636,7 +1636,7 @@ void ARMAsmPrinter::EmitKCFI_CHECK_ARM32(Register AddrReg, int64_t Type,
.addImm(SOImmVal)
.addImm(ARMCC::AL)
.addReg(0)
- .addReg(isLast ? ARM::CPSR : ARM::NoRegister));
+ .addReg(isLast ? ARM::CPSR : Register()));
}
// If we spilled r3, restore it immediately after the comparison.
@@ -1734,7 +1734,7 @@ void ARMAsmPrinter::EmitKCFI_CHECK_Thumb2(Register AddrReg, int64_t Type,
.addImm(imm)
.addImm(ARMCC::AL)
.addReg(0)
- .addReg(isLast ? ARM::CPSR : ARM::NoRegister));
+ .addReg(isLast ? ARM::CPSR : Register()));
}
// If we spilled r3, restore it immediately after the comparison.
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index dad034ede1dd4..42b8977e3acea 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -450,7 +450,7 @@ bool ARMBaseInstrInfo::PredicateInstruction(
assert((MI.getOperand(1).isDead() ||
MI.getOperand(1).getReg() != ARM::CPSR) &&
"if conversion tried to stop defining used CPSR");
- MI.getOperand(1).setReg(ARM::NoRegister);
+ MI.getOperand(1).setReg(Register());
}
return true;
@@ -6589,7 +6589,7 @@ class ARMPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
.addReg(LoopDec->getOperand(0).getReg())
.addImm(0)
.addImm(ARMCC::AL)
- .addReg(ARM::NoRegister);
+ .addReg(Register());
Cond.push_back(MachineOperand::CreateImm(ARMCC::EQ));
Cond.push_back(MachineOperand::CreateReg(ARM::CPSR, false));
return {};
diff --git a/llvm/lib/Target/ARM/ARMBlockPlacement.cpp b/llvm/lib/Target/ARM/ARMBlockPlacement.cpp
index 3d8ebfeae81da..c258f37fa9906 100644
--- a/llvm/lib/Target/ARM/ARMBlockPlacement.cpp
+++ b/llvm/lib/Target/ARM/ARMBlockPlacement.cpp
@@ -278,7 +278,7 @@ void ARMBlockPlacement::moveBasicBlock(MachineBasicBlock *BB,
BuildMI(From, Terminator.getDebugLoc(), TII->get(ARM::t2B));
MIB.addMBB(To);
MIB.addImm(ARMCC::CondCodes::AL);
- MIB.addReg(ARM::NoRegister);
+ MIB.addReg(Register());
LLVM_DEBUG(dbgs() << DEBUG_PREFIX << "Adding unconditional branch from "
<< From->getName() << " to " << To->getName() << ": "
<< *MIB.getInstr());
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 91fd2129a5d0b..b7b47a2542277 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1298,7 +1298,7 @@ ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB,
if (!Op.isReg())
continue;
Register Reg = Op.getReg();
- if (Reg == ARM::NoRegister || Reg == ARM::LR)
+ if (!Reg.isValid() || Reg == ARM::LR)
continue;
assert(Reg.isPhysical() && "Unallocated register");
ClearBB->addLiveIn(Reg);
diff --git a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
index 547205f900039..d32b413880a87 100644
--- a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
+++ b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
@@ -415,7 +415,7 @@ void ARMFixCortexA57AES1742098::insertAESFixup(
.addReg(RegToFixup, RegState::Kill | Renamable)
.addReg(RegToFixup, RegState::Kill | Renamable)
.addImm((uint64_t)ARMCC::AL)
- .addReg(ARM::NoRegister);
+ .addReg(Register());
}
// Factory function used by AArch64TargetMachine to add the pass to
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 058033bb7e942..f25bcf30e00da 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1804,7 +1804,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
bool OddUndef = MI->getOperand(1).isUndef();
bool BaseKill = BaseOp.isKill();
bool BaseUndef = BaseOp.isUndef();
- assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) &&
+ assert((isT2 || !MI->getOperand(3).getReg().isValid()) &&
"register offset not handled below");
int OffImm = getMemoryOpOffset(*MI);
Register PredReg;
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index f89f209d6ecf8..3635fb3da020c 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -1475,7 +1475,7 @@ void ARMLowOverheadLoops::RevertLoopEndDec(MachineInstr *MI) const {
MIB.add(MI->getOperand(1));
MIB.addImm(1);
MIB.addImm(ARMCC::AL);
- MIB.addReg(ARM::NoRegister);
+ MIB.addReg(Register());
MIB.addReg(ARM::CPSR);
MIB->getOperand(5).setIsDef(true);
diff --git a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
index 9295aaf574daa..4974e0759595c 100644
--- a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
+++ b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
@@ -197,7 +197,7 @@ static void RevertWhileLoopSetup(MachineInstr *MI, const TargetInstrInfo *TII) {
MIB.add(MI->getOperand(1));
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
- MIB.addReg(ARM::NoRegister);
+ MIB.addReg(Register());
MIB.addReg(ARM::CPSR, RegState::Define);
// Attempt to find a t2WhileLoopStart and revert to a t2Bcc.
diff --git a/llvm/lib/Target/ARM/MVETailPredUtils.h b/llvm/lib/Target/ARM/MVETailPredUtils.h
index 8c64893d448f1..083c6f69a6357 100644
--- a/llvm/lib/Target/ARM/MVETailPredUtils.h
+++ b/llvm/lib/Target/ARM/MVETailPredUtils.h
@@ -110,7 +110,7 @@ inline void RevertWhileLoopStartLR(MachineInstr *MI, const TargetInstrInfo *TII,
MIB.add(MI->getOperand(1));
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
- MIB.addReg(ARM::NoRegister);
+ MIB.addReg(Register());
} else {
MachineInstrBuilder MIB =
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
@@ -118,7 +118,7 @@ inline void RevertWhileLoopStartLR(MachineInstr *MI, const TargetInstrInfo *TII,
MIB.add(MI->getOperand(1));
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
- MIB.addReg(ARM::NoRegister);
+ MIB.addReg(Register());
MIB.addReg(ARM::CPSR, RegState::Define);
}
@@ -175,7 +175,7 @@ inline void RevertLoopEnd(MachineInstr *MI, const TargetInstrInfo *TII,
MIB.add(MI->getOperand(0));
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
- MIB.addReg(ARM::NoRegister);
+ MIB.addReg(Register());
}
// Create bne
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index de4eadf955ab9..41c7138621bc1 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -65,7 +65,7 @@ emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
const TargetInstrInfo &TII, const DebugLoc &dl,
const ThumbRegisterInfo &MRI, int NumBytes,
- unsigned ScratchReg, unsigned MIFlags) {
+ Register ScratchReg, unsigned MIFlags) {
// If it would take more than three instructions to adjust the stack pointer
// using tADDspi/tSUBspi, load an immediate instead.
if (std::abs(NumBytes) > 508 * 3) {
@@ -73,7 +73,7 @@ emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB,
// emitThumbRegPlusImmediate so we don't have to deal with register
// scavenging. (Scavenging could try to use the emergency spill slot
// before we've actually finished setting up the stack.)
- if (ScratchReg == ARM::NoRegister)
+ if (!ScratchReg.isValid())
report_fatal_error("Failed to emit Thumb1 stack adjustment");
MachineFunction &MF = *MBB.getParent();
const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
@@ -96,7 +96,6 @@ emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB,
// won't change.
emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
MRI, MIFlags);
-
}
static void emitCallSPUpdate(MachineBasicBlock &MBB,
@@ -180,7 +179,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
if (ArgRegsSaveSize) {
emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
- ARM::NoRegister, MachineInstr::FrameSetup);
+ Register(), MachineInstr::FrameSetup);
CFAOffset += ArgRegsSaveSize;
CFIBuilder.buildDefCFAOffset(CFAOffset);
}
@@ -188,8 +187,8 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
if (!AFI->hasStackFrame()) {
if (NumBytes - ArgRegsSaveSize != 0) {
emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
- -(NumBytes - ArgRegsSaveSize),
- ARM::NoRegister, MachineInstr::FrameSetup);
+ -(NumBytes - ArgRegsSaveSize), Register(),
+ MachineInstr::FrameSetup);
CFAOffset += NumBytes - ArgRegsSaveSize;
CFIBuilder.buildDefCFAOffset(CFAOffset);
}
@@ -394,7 +393,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
// For a large stack frame, we might need a scratch register to store
// the size of the frame. We know all callee-save registers are free
// at this point in the prologue, so pick one.
- unsigned ScratchRegister = ARM::NoRegister;
+ Register ScratchRegister;
for (auto &I : CSI) {
MCRegister Reg = I.getReg();
if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr.asMCReg())) {
@@ -489,7 +488,7 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
if (!AFI->hasStackFrame()) {
if (NumBytes - ArgRegsSaveSize != 0)
emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
- NumBytes - ArgRegsSaveSize, ARM::NoRegister,
+ NumBytes - ArgRegsSaveSize, Register(),
MachineInstr::FrameDestroy);
} else {
// Unwind MBBI to point to first LDR / VLDRD.
@@ -509,7 +508,7 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
// We are likely to need a scratch register and we know all callee-save
// registers are free at this point in the epilogue, so pick one.
- unsigned ScratchRegister = ARM::NoRegister;
+ Register ScratchRegister;
bool HasFP = hasFP(MF);
for (auto &I : MFI.getCalleeSavedInfo()) {
MCRegister Reg = I.getReg();
@@ -525,7 +524,7 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
// frame pointer stack slot, the target is ELF and the function has FP, or
// the target uses var sized objects.
if (NumBytes) {
- assert(ScratchRegister != ARM::NoRegister &&
+ assert(ScratchRegister.isValid() &&
"No scratch register to restore SP from FP!");
emitThumbRegPlusImmediate(MBB, MBBI, dl, ScratchRegister, FramePtr, -NumBytes,
TII, *RegInfo, MachineInstr::FrameDestroy);
@@ -735,7 +734,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
MBBI++;
// Increment the SP.
emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo,
- ArgRegsSaveSize + 4, ARM::NoRegister,
+ ArgRegsSaveSize + 4, Register(),
MachineInstr::FrameDestroy);
return true;
}
@@ -782,7 +781,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
.setMIFlag(MachineInstr::FrameDestroy);
emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize,
- ARM::NoRegister, MachineInstr::FrameDestroy);
+ Register(), MachineInstr::FrameDestroy);
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
.addReg(ARM::LR, RegState::Define)
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index ef67e1116af72..bb10cc60b54a8 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -83,7 +83,7 @@ void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
BitVector Allocatable = RegInfo->getAllocatableSet(
MF, RegInfo->getRegClass(ARM::hGPRRegClassID));
- Register TmpReg = ARM::NoRegister;
+ Register TmpReg;
// Prefer R12 as it is known to not be preserved anyway
if (UsedRegs.available(ARM::R12) && Allocatable.test(ARM::R12)) {
TmpReg = ARM::R12;
>From eecc63d69da63f5710ba902e2635ddcc169cf1b5 Mon Sep 17 00:00:00 2001
From: Jan Rehders <jrehders at baylibre.com>
Date: Tue, 15 Sep 2026 21:10:04 +0200
Subject: [PATCH 2/3] [ARM] Replace unsigned with Register NFC
---
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 103 ++++++++++---------
1 file changed, 53 insertions(+), 50 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index b7b47a2542277..4d2d5aebbf421 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -83,8 +83,8 @@ namespace {
MachineBasicBlock::iterator &MBBI);
void CMSEClearGPRegs(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
- const SmallVectorImpl<unsigned> &ClearRegs,
- unsigned ClobberReg);
+ const SmallVectorImpl<Register> &ClearRegs,
+ Register ClobberReg);
MachineBasicBlock &CMSEClearFPRegs(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI);
MachineBasicBlock &CMSEClearFPRegsV8(MachineBasicBlock &MBB,
@@ -96,23 +96,23 @@ namespace {
void CMSESaveClearFPRegs(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc &DL,
const LivePhysRegs &LiveRegs,
- SmallVectorImpl<unsigned> &AvailableRegs);
+ SmallVectorImpl<Register> &AvailableRegs);
void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc &DL,
const LivePhysRegs &LiveRegs,
- SmallVectorImpl<unsigned> &ScratchRegs);
+ SmallVectorImpl<Register> &ScratchRegs);
void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc &DL,
const LivePhysRegs &LiveRegs);
void CMSERestoreFPRegs(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- SmallVectorImpl<unsigned> &AvailableRegs);
+ SmallVectorImpl<Register> &AvailableRegs);
void CMSERestoreFPRegsV8(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- SmallVectorImpl<unsigned> &AvailableRegs);
+ SmallVectorImpl<Register> &AvailableRegs);
void CMSERestoreFPRegsV81(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- SmallVectorImpl<unsigned> &AvailableRegs);
+ SmallVectorImpl<Register> &AvailableRegs);
bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
unsigned StrexOp, unsigned UxtOp,
@@ -522,7 +522,7 @@ static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
/// corresponding to the specified register spacing. Not all of the results
/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
-static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
+static void GetDSubRegs(Register Reg, NEONRegSpacing RegSpc,
const TargetRegisterInfo *TRI, MCRegister &D0,
MCRegister &D1, MCRegister &D2, MCRegister &D3) {
if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
@@ -777,7 +777,7 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
MCRegister D0, D1, D2, D3;
- unsigned DstReg = 0;
+ Register DstReg = 0;
bool DstIsDead = false;
if (TableEntry->IsLoad) {
DstIsDead = MI.getOperand(OpIdx).isDead();
@@ -1171,8 +1171,8 @@ static const int CMSE_FP_SAVE_SIZE = 136;
static void determineGPRegsToClear(const MachineInstr &MI,
const std::initializer_list<unsigned> &Regs,
- SmallVectorImpl<unsigned> &ClearRegs) {
- SmallVector<unsigned, 4> OpRegs;
+ SmallVectorImpl<Register> &ClearRegs) {
+ SmallVector<Register, 4> OpRegs;
for (const MachineOperand &Op : MI.operands()) {
if (!Op.isReg() || !Op.isUse())
continue;
@@ -1186,21 +1186,21 @@ static void determineGPRegsToClear(const MachineInstr &MI,
void ARMExpandPseudo::CMSEClearGPRegs(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, const SmallVectorImpl<unsigned> &ClearRegs,
- unsigned ClobberReg) {
+ const DebugLoc &DL, const SmallVectorImpl<Register> &ClearRegs,
+ Register ClobberReg) {
if (STI->hasV8_1MMainlineOps()) {
// Clear the registers using the CLRM instruction.
MachineInstrBuilder CLRM =
BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL));
- for (unsigned R : ClearRegs)
+ for (Register R : ClearRegs)
CLRM.addReg(R, RegState::Define);
CLRM.addReg(ARM::APSR, RegState::Define);
CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
} else {
// Clear the registers and flags by copying ClobberReg into them.
// (Baseline can't do a high register clear in one instruction).
- for (unsigned Reg : ClearRegs) {
+ for (Register Reg : ClearRegs) {
if (Reg == ClobberReg)
continue;
BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg)
@@ -1411,7 +1411,7 @@ ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB,
void ARMExpandPseudo::CMSESaveClearFPRegs(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
+ const LivePhysRegs &LiveRegs, SmallVectorImpl<Register> &ScratchRegs) {
if (STI->hasV8_1MMainlineOps())
CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
else if (STI->hasV8MMainlineOps())
@@ -1421,11 +1421,11 @@ void ARMExpandPseudo::CMSESaveClearFPRegs(
// Save and clear FP registers if present
void ARMExpandPseudo::CMSESaveClearFPRegsV8(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
+ const LivePhysRegs &LiveRegs, SmallVectorImpl<Register> &ScratchRegs) {
// Store an available register for FPSCR clearing
assert(!ScratchRegs.empty());
- unsigned SpareReg = ScratchRegs.front();
+ Register SpareReg = ScratchRegs.front();
// save space on stack for VLSTM
BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
@@ -1434,8 +1434,8 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
.add(predOps(ARMCC::AL));
// Use ScratchRegs to store the fp regs
- std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
- std::vector<unsigned> NonclearedFPRegs;
+ std::vector<std::tuple<Register, Register, Register>> ClearedFPRegs;
+ std::vector<Register> NonclearedFPRegs;
bool ReturnsFPReg = false;
for (const MachineOperand &Op : MBBI->operands()) {
if (Op.isReg() && Op.isUse()) {
@@ -1445,8 +1445,8 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
assert(!ARM::QPRRegClass.contains(Reg));
if (ARM::DPR_VFP2RegClass.contains(Reg)) {
if (ScratchRegs.size() >= 2) {
- unsigned SaveReg2 = ScratchRegs.pop_back_val();
- unsigned SaveReg1 = ScratchRegs.pop_back_val();
+ Register SaveReg2 = ScratchRegs.pop_back_val();
+ Register SaveReg1 = ScratchRegs.pop_back_val();
ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
// Save the fp register to the normal registers
@@ -1460,8 +1460,8 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
}
} else if (ARM::SPRRegClass.contains(Reg)) {
if (ScratchRegs.size() >= 1) {
- unsigned SaveReg = ScratchRegs.pop_back_val();
- ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
+ Register SaveReg = ScratchRegs.pop_back_val();
+ ClearedFPRegs.emplace_back(Reg, SaveReg, Register());
// Save the fp register to the normal registers
BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
@@ -1534,7 +1534,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
// Restore all arguments
for (const auto &Regs : ClearedFPRegs) {
- unsigned Reg, SaveReg1, SaveReg2;
+ Register Reg, SaveReg1, SaveReg2;
std::tie(Reg, SaveReg1, SaveReg2) = Regs;
if (ARM::DPR_VFP2RegClass.contains(Reg))
BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
@@ -1547,7 +1547,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
.add(predOps(ARMCC::AL));
}
- for (unsigned Reg : NonclearedFPRegs) {
+ for (Register Reg : NonclearedFPRegs) {
if (ARM::DPR_VFP2RegClass.contains(Reg)) {
if (STI->isLittle()) {
BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg)
@@ -1637,7 +1637,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP)
.addReg(ARM::SP)
.add(predOps(ARMCC::AL));
- for (unsigned Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
+ for (Register Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
VPUSH.addReg(Reg);
// Clear FP registers with a VSCCLRM.
@@ -1654,7 +1654,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
// Restore FP registers if present
void ARMExpandPseudo::CMSERestoreFPRegs(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- SmallVectorImpl<unsigned> &AvailableRegs) {
+ SmallVectorImpl<Register> &AvailableRegs) {
if (STI->hasV8_1MMainlineOps())
CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs);
else if (STI->hasV8MMainlineOps())
@@ -1663,16 +1663,16 @@ void ARMExpandPseudo::CMSERestoreFPRegs(
void ARMExpandPseudo::CMSERestoreFPRegsV8(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- SmallVectorImpl<unsigned> &AvailableRegs) {
+ SmallVectorImpl<Register> &AvailableRegs) {
// Keep a scratch register for the mitigation sequence.
- unsigned ScratchReg = ARM::NoRegister;
+ Register ScratchReg;
if (STI->fixCMSE_CVE_2021_35465())
ScratchReg = AvailableRegs.pop_back_val();
// Use AvailableRegs to store the fp regs
- std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
- std::vector<unsigned> NonclearedFPRegs;
+ std::vector<std::tuple<Register, Register, Register>> ClearedFPRegs;
+ std::vector<Register> NonclearedFPRegs;
for (const MachineOperand &Op : MBBI->operands()) {
if (Op.isReg() && Op.isDef()) {
Register Reg = Op.getReg();
@@ -1681,8 +1681,8 @@ void ARMExpandPseudo::CMSERestoreFPRegsV8(
assert(!ARM::QPRRegClass.contains(Reg));
if (ARM::DPR_VFP2RegClass.contains(Reg)) {
if (AvailableRegs.size() >= 2) {
- unsigned SaveReg2 = AvailableRegs.pop_back_val();
- unsigned SaveReg1 = AvailableRegs.pop_back_val();
+ Register SaveReg2 = AvailableRegs.pop_back_val();
+ Register SaveReg1 = AvailableRegs.pop_back_val();
ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
// Save the fp register to the normal registers
@@ -1696,7 +1696,7 @@ void ARMExpandPseudo::CMSERestoreFPRegsV8(
}
} else if (ARM::SPRRegClass.contains(Reg)) {
if (AvailableRegs.size() >= 1) {
- unsigned SaveReg = AvailableRegs.pop_back_val();
+ Register SaveReg = AvailableRegs.pop_back_val();
ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
// Save the fp register to the normal registers
@@ -1716,7 +1716,7 @@ void ARMExpandPseudo::CMSERestoreFPRegsV8(
assert(STI->hasFPRegs() && "Subtarget needs fpregs");
// Push FP regs that cannot be restored via normal registers on the stack
- for (unsigned Reg : NonclearedFPRegs) {
+ for (Register Reg : NonclearedFPRegs) {
if (ARM::DPR_VFP2RegClass.contains(Reg))
BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD))
.addReg(Reg)
@@ -1774,7 +1774,7 @@ void ARMExpandPseudo::CMSERestoreFPRegsV8(
// Restore all FP registers via normal registers
for (const auto &Regs : ClearedFPRegs) {
- unsigned Reg, SaveReg1, SaveReg2;
+ Register Reg, SaveReg1, SaveReg2;
std::tie(Reg, SaveReg1, SaveReg2) = Regs;
if (ARM::DPR_VFP2RegClass.contains(Reg))
BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
@@ -1809,7 +1809,7 @@ static bool definesOrUsesFPReg(const MachineInstr &MI) {
void ARMExpandPseudo::CMSERestoreFPRegsV81(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
- SmallVectorImpl<unsigned> &AvailableRegs) {
+ SmallVectorImpl<Register> & /*AvailableRegs*/) {
if (!definesOrUsesFPReg(*MBBI)) {
if (STI->fixCMSE_CVE_2021_35465()) {
BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS))
@@ -1842,7 +1842,7 @@ void ARMExpandPseudo::CMSERestoreFPRegsV81(
BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP)
.addReg(ARM::SP)
.add(predOps(ARMCC::AL));
- for (unsigned Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
+ for (Register Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
VPOP.addReg(Reg, RegState::Define);
}
}
@@ -2110,7 +2110,7 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
if (Thumb1Only) { // push Lo and Hi regs separately
MachineInstrBuilder PushMIB =
BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
- for (unsigned Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
+ for (Register Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
PushMIB.addReg(
Reg, getUndefRegState(Reg != JumpReg && !LiveRegs.contains(Reg)));
}
@@ -2122,18 +2122,21 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
// memory, and allow us to later pop them with a single instructions.
// FIXME: Could also use any of r0-r3 that are free (including in the
// first PUSH above).
- for (unsigned LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4;
- --LoReg) {
+ const Register LoRegs[] = {ARM::R7, ARM::R6, ARM::R5, ARM::R4};
+ const Register HiRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
+ unsigned HiIdx = 0;
+ for (Register LoReg : LoRegs) {
if (JumpReg == LoReg)
continue;
BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
- .addReg(HiReg, getUndefRegState(!LiveRegs.contains(HiReg)))
+ .addReg(HiRegs[HiIdx],
+ getUndefRegState(!LiveRegs.contains(HiRegs[HiIdx])))
.add(predOps(ARMCC::AL));
- --HiReg;
+ ++HiIdx;
}
MachineInstrBuilder PushMIB2 =
BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
- for (unsigned Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
+ for (Register Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
if (Reg == JumpReg)
continue;
PushMIB2.addReg(Reg, RegState::Kill);
@@ -2156,7 +2159,7 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
.addReg(ARM::SP)
.add(predOps(ARMCC::AL));
- for (unsigned Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
+ for (Register Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
PushMIB.addReg(
Reg, getUndefRegState(Reg != JumpReg && !LiveRegs.contains(Reg)));
}
@@ -2186,7 +2189,7 @@ static void CMSEPopCalleeSaves(const TargetInstrInfo &TII,
BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP)
.addReg(ARM::SP)
.add(predOps(ARMCC::AL));
- for (unsigned Reg = ARM::R4; Reg < ARM::R12; ++Reg)
+ for (Register Reg = ARM::R4; Reg < ARM::R12; ++Reg)
PopMIB.addReg(Reg, RegState::Define);
}
}
@@ -2366,7 +2369,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) {
return !Op.isReg() || Op.getReg() != ARM::R12;
}));
- SmallVector<unsigned, 5> ClearRegs;
+ SmallVector<Register, 5> ClearRegs;
determineGPRegsToClear(
*MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs,
@@ -2399,7 +2402,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs,
AFI->isThumb1OnlyFunction());
- SmallVector<unsigned, 16> ClearRegs;
+ SmallVector<Register, 16> ClearRegs;
determineGPRegsToClear(*MBBI,
{ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9,
@@ -2409,7 +2412,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
// Get the first cleared register as a scratch (to use later with tBIC).
// We need to use the first so we can ensure it is a low register.
- unsigned ScratchReg = ClearRegs.front();
+ Register ScratchReg = ClearRegs.front();
// Clear LSB of JumpReg
if (AFI->isThumb2Function()) {
>From 3955e65b10f03261006b05c58c7606c3234529ac Mon Sep 17 00:00:00 2001
From: Jan Rehders <jrehders at baylibre.com>
Date: Thu, 17 Sep 2026 13:09:34 +0200
Subject: [PATCH 3/3] [ARM] clang-format for previously changed files NFC
---
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 30 ++++++++++-----------
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 17 ++++++------
2 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index bb8c99d591a35..ef21aa3ba6adf 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1629,14 +1629,13 @@ void ARMAsmPrinter::EmitKCFI_CHECK_ARM32(Register AddrReg, int64_t Type,
"Cannot encode immediate as ARM modified immediate");
// eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
- EmitToStreamer(*OutStreamer,
- MCInstBuilder(ARM::EORri)
- .addReg(ScratchReg)
- .addReg(ScratchReg)
- .addImm(SOImmVal)
- .addImm(ARMCC::AL)
- .addReg(0)
- .addReg(isLast ? ARM::CPSR : Register()));
+ EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::EORri)
+ .addReg(ScratchReg)
+ .addReg(ScratchReg)
+ .addImm(SOImmVal)
+ .addImm(ARMCC::AL)
+ .addReg(0)
+ .addReg(isLast ? ARM::CPSR : Register()));
}
// If we spilled r3, restore it immediately after the comparison.
@@ -1727,14 +1726,13 @@ void ARMAsmPrinter::EmitKCFI_CHECK_Thumb2(Register AddrReg, int64_t Type,
"Cannot encode immediate as Thumb2 modified immediate");
// eor[s] scratch, scratch, #imm (last one sets flags with CPSR)
- EmitToStreamer(*OutStreamer,
- MCInstBuilder(ARM::t2EORri)
- .addReg(ScratchReg)
- .addReg(ScratchReg)
- .addImm(imm)
- .addImm(ARMCC::AL)
- .addReg(0)
- .addReg(isLast ? ARM::CPSR : Register()));
+ EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2EORri)
+ .addReg(ScratchReg)
+ .addReg(ScratchReg)
+ .addImm(imm)
+ .addImm(ARMCC::AL)
+ .addReg(0)
+ .addReg(isLast ? ARM::CPSR : Register()));
}
// If we spilled r3, restore it immediately after the comparison.
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index 41c7138621bc1..49b5aa5703d77 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -60,12 +60,13 @@ bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
return !MFI.hasVarSizedObjects();
}
-static void
-emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo &TII, const DebugLoc &dl,
- const ThumbRegisterInfo &MRI, int NumBytes,
- Register ScratchReg, unsigned MIFlags) {
+static void emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator &MBBI,
+ const TargetInstrInfo &TII,
+ const DebugLoc &dl,
+ const ThumbRegisterInfo &MRI,
+ int NumBytes, Register ScratchReg,
+ unsigned MIFlags) {
// If it would take more than three instructions to adjust the stack pointer
// using tADDspi/tSUBspi, load an immediate instead.
if (std::abs(NumBytes) > 508 * 3) {
@@ -94,8 +95,8 @@ emitPrologueEpilogueSPUpdate(MachineBasicBlock &MBB,
}
// FIXME: This is assuming the heuristics in emitThumbRegPlusImmediate
// won't change.
- emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
- MRI, MIFlags);
+ emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, MRI,
+ MIFlags);
}
static void emitCallSPUpdate(MachineBasicBlock &MBB,
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