[clang] [llvm] [X86] Add ACE v1 (AI Compute Extensions) support (PR #208408)

[via llvm-commits]

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@@ -857,6 +859,13 @@ let CopyCost = -1 in // Don't allow copying of tile registers
 def TILE : RegisterClass<"X86", [x86amx], 8192,
                          (sequence "TMM%u", 0, 7)> {let Size = 8192;}
 
+// Block Scale Registers (ACE)
+let CopyCost = -1 in // Don't allow copying of BSR register
+def BSR : RegisterClass<"X86", [untyped], 0, (add BSR0)> {
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ganeshgit wrote:

This is a wrapper. I removed it since we need to handle BSR0 as a register for now and not as a class similar to TMMCFG. 

https://github.com/llvm/llvm-project/pull/208408