[llvm] [IR][REVEC] Define llvm.vector.repeat intrinsic (PR #208212)

[Benjamin Maxwell via llvm-commits]

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In-Reply-To: <llvm.org/llvm/llvm-project/pull/208212 at github.com>


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@@ -6062,6 +6079,19 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
   return DAG.getNode(N->getOpcode(), dl, OutVT, V0, V1, N->getOperand(2));
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REPEAT(SDNode *N) {
+  SDLoc DL(N);
+
+  EVT OutVT = N->getValueType(0);
+  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
+  assert(NOutVT.isVector() && "This type must be promoted to a vector type");
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MacDue wrote:

I guess this assert can be removed then?

https://github.com/llvm/llvm-project/pull/208212