[llvm] [SelectionDAG][AMDGPU] Fold mul24 with an AND operand whose low bits are zero (PR #224537)

[Simon Pilgrim via llvm-commits]

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@@ -826,6 +826,11 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
     LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
 
+    // If either operand is known zero for every demanded bit, the result is
+    // zero.
+    if (DemandedBits.isSubsetOf(LHSKnown.Zero | RHSKnown.Zero))
+      return DAG.getConstant(0, SDLoc(Op), VT);
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RKSimon wrote:

Why isn't the general SimplifyDemandedBits catching this?

https://github.com/llvm/llvm-project/pull/224537