[clang] [llvm] [RISCV][P-ext] Support Packed Multiply High Parts (PR #225015)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 01:35:53 PDT 2026
https://github.com/TelGome updated https://github.com/llvm/llvm-project/pull/225015
>From dc011bf519c4b85292beff555083a51dd6aa117c Mon Sep 17 00:00:00 2001
From: Dongyan Chen <chendongyan at isrc.iscas.ac.cn>
Date: Mon, 21 Sep 2026 06:25:57 +0000
Subject: [PATCH 1/3] [RISCV][P-ext] Support Packed Multiply High Parts
Support the RISC-V P packed multiply-high-parts instructions, which
multiply the full-width element of rs1 by one byte (b0/b1) or one
halfword (h0/h1) of the corresponding element of rs2 and keep the
high half of each product.
---
clang/include/clang/Basic/BuiltinsRISCV.td | 20 +
clang/lib/CodeGen/TargetBuiltins/RISCV.cpp | 68 +++-
clang/lib/Headers/riscv_packed_simd.h | 20 +
clang/test/CodeGen/RISCV/rvp-intrinsics.c | 345 +++++++++++++++++-
.../riscv_packed_simd.c | 109 ++++++
llvm/include/llvm/IR/IntrinsicsRISCV.td | 28 ++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 193 ++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 58 +++
llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 93 +++++
llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 121 ++++++
10 files changed, 1051 insertions(+), 4 deletions(-)
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index ee840e45a65ba..9065e9e363a56 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -404,6 +404,26 @@ def mulu_w11_u64 : RISCVBuiltin<"uint64_t(_Vector<2, unsigned int>, _Vector<2, u
def mulsu_w00_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, unsigned int>)">;
def mulsu_w11_i64 : RISCVBuiltin<"int64_t(_Vector<2, int>, _Vector<2, unsigned int>)">;
+// Packed Multiply High Parts (32-bit)
+def pmulh_b0_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, signed char>)">;
+def pmulh_b1_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, signed char>)">;
+def pmulhsu_b0_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, unsigned char>)">;
+def pmulhsu_b1_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<4, unsigned char>)">;
+def mulh_h0_i32 : RISCVBuiltin<"int(int, _Vector<2, short>)">;
+def mulh_h1_i32 : RISCVBuiltin<"int(int, _Vector<2, short>)">;
+def mulhsu_h0_i32 : RISCVBuiltin<"int(int, _Vector<2, unsigned short>)">;
+def mulhsu_h1_i32 : RISCVBuiltin<"int(int, _Vector<2, unsigned short>)">;
+
+// Packed Multiply High Parts (64-bit)
+def pmulh_b0_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, signed char>)">;
+def pmulh_b1_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, signed char>)">;
+def pmulhsu_b0_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, unsigned char>)">;
+def pmulhsu_b1_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<8, unsigned char>)">;
+def pmulh_h0_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>)">;
+def pmulh_h1_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, short>)">;
+def pmulhsu_h0_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, unsigned short>)">;
+def pmulhsu_h1_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<4, unsigned short>)">;
+
// Packed "Q-format" Multiply Parts Accumulate (32-bit)
def mqacc_h00_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">;
def mqacc_h01_i32 : RISCVBuiltin<"int(int, _Vector<2, short>, _Vector<2, short>)">;
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index f99a05ce673aa..82c69f5d87dcf 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1759,7 +1759,19 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_pmulu_h01_u32x2:
case RISCV::BI__builtin_riscv_pmulu_h11_u32x2:
case RISCV::BI__builtin_riscv_pmulsu_h00_i32x2:
- case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2: {
+ case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2:
+ case RISCV::BI__builtin_riscv_pmulh_b0_i16x2:
+ case RISCV::BI__builtin_riscv_pmulh_b1_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2:
+ case RISCV::BI__builtin_riscv_pmulh_b0_i16x4:
+ case RISCV::BI__builtin_riscv_pmulh_b1_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4:
+ case RISCV::BI__builtin_riscv_pmulh_h0_i32x2:
+ case RISCV::BI__builtin_riscv_pmulh_h1_i32x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2: {
switch (BuiltinID) {
default:
llvm_unreachable("unexpected builtin ID");
@@ -1803,6 +1815,34 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_pmulsu_h11_i32x2:
ID = Intrinsic::riscv_pmulsu_11;
break;
+ case RISCV::BI__builtin_riscv_pmulh_b0_i16x2:
+ case RISCV::BI__builtin_riscv_pmulh_b0_i16x4:
+ ID = Intrinsic::riscv_pmulh_b0;
+ break;
+ case RISCV::BI__builtin_riscv_pmulh_b1_i16x2:
+ case RISCV::BI__builtin_riscv_pmulh_b1_i16x4:
+ ID = Intrinsic::riscv_pmulh_b1;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_b0_i16x4:
+ ID = Intrinsic::riscv_pmulhsu_b0;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_b1_i16x4:
+ ID = Intrinsic::riscv_pmulhsu_b1;
+ break;
+ case RISCV::BI__builtin_riscv_pmulh_h0_i32x2:
+ ID = Intrinsic::riscv_pmulh_h0;
+ break;
+ case RISCV::BI__builtin_riscv_pmulh_h1_i32x2:
+ ID = Intrinsic::riscv_pmulh_h1;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhsu_h0_i32x2:
+ ID = Intrinsic::riscv_pmulhsu_h0;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhsu_h1_i32x2:
+ ID = Intrinsic::riscv_pmulhsu_h1;
+ break;
}
IntrinsicTypes = {ResultType};
@@ -1867,6 +1907,32 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
break;
}
+ // Scalar Multiply High Parts
+ case RISCV::BI__builtin_riscv_mulh_h0_i32:
+ case RISCV::BI__builtin_riscv_mulh_h1_i32:
+ case RISCV::BI__builtin_riscv_mulhsu_h0_i32:
+ case RISCV::BI__builtin_riscv_mulhsu_h1_i32: {
+ switch (BuiltinID) {
+ default:
+ llvm_unreachable("unexpected builtin ID");
+ case RISCV::BI__builtin_riscv_mulh_h0_i32:
+ ID = Intrinsic::riscv_mulh_h0;
+ break;
+ case RISCV::BI__builtin_riscv_mulh_h1_i32:
+ ID = Intrinsic::riscv_mulh_h1;
+ break;
+ case RISCV::BI__builtin_riscv_mulhsu_h0_i32:
+ ID = Intrinsic::riscv_mulhsu_h0;
+ break;
+ case RISCV::BI__builtin_riscv_mulhsu_h1_i32:
+ ID = Intrinsic::riscv_mulhsu_h1;
+ break;
+ }
+
+ IntrinsicTypes = {ResultType, Ops[1]->getType()};
+ break;
+ }
+
// Packed "Q-format" Multiply Parts Accumulate
case RISCV::BI__builtin_riscv_mqacc_h00_i32:
case RISCV::BI__builtin_riscv_mqacc_h01_i32:
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index db6d0d37c2e8a..2cee5987c1dac 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -1079,6 +1079,26 @@ __packed_binary_builtin_mixed(mulu_w11_u64, uint64_t, uint32x2_t, uint32x2_t, __
__packed_binary_builtin_mixed(mulsu_w00_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_mulsu_w00_i64)
__packed_binary_builtin_mixed(mulsu_w11_i64, int64_t, int32x2_t, uint32x2_t, __builtin_riscv_mulsu_w11_i64)
+/* Packed Multiply High Parts (32-bit) */
+__packed_binary_builtin_mixed(pmulh_b0_i16x2, int16x2_t, int16x2_t, int8x4_t, __builtin_riscv_pmulh_b0_i16x2)
+__packed_binary_builtin_mixed(pmulh_b1_i16x2, int16x2_t, int16x2_t, int8x4_t, __builtin_riscv_pmulh_b1_i16x2)
+__packed_binary_builtin_mixed(pmulhsu_b0_i16x2, int16x2_t, int16x2_t, uint8x4_t, __builtin_riscv_pmulhsu_b0_i16x2)
+__packed_binary_builtin_mixed(pmulhsu_b1_i16x2, int16x2_t, int16x2_t, uint8x4_t, __builtin_riscv_pmulhsu_b1_i16x2)
+__packed_binary_builtin_mixed(mulh_h0_i32, int32_t, int32_t, int16x2_t, __builtin_riscv_mulh_h0_i32)
+__packed_binary_builtin_mixed(mulh_h1_i32, int32_t, int32_t, int16x2_t, __builtin_riscv_mulh_h1_i32)
+__packed_binary_builtin_mixed(mulhsu_h0_i32, int32_t, int32_t, uint16x2_t, __builtin_riscv_mulhsu_h0_i32)
+__packed_binary_builtin_mixed(mulhsu_h1_i32, int32_t, int32_t, uint16x2_t, __builtin_riscv_mulhsu_h1_i32)
+
+/* Packed Multiply High Parts (64-bit) */
+__packed_binary_builtin_mixed(pmulh_b0_i16x4, int16x4_t, int16x4_t, int8x8_t, __builtin_riscv_pmulh_b0_i16x4)
+__packed_binary_builtin_mixed(pmulh_b1_i16x4, int16x4_t, int16x4_t, int8x8_t, __builtin_riscv_pmulh_b1_i16x4)
+__packed_binary_builtin_mixed(pmulhsu_b0_i16x4, int16x4_t, int16x4_t, uint8x8_t, __builtin_riscv_pmulhsu_b0_i16x4)
+__packed_binary_builtin_mixed(pmulhsu_b1_i16x4, int16x4_t, int16x4_t, uint8x8_t, __builtin_riscv_pmulhsu_b1_i16x4)
+__packed_binary_builtin_mixed(pmulh_h0_i32x2, int32x2_t, int32x2_t, int16x4_t, __builtin_riscv_pmulh_h0_i32x2)
+__packed_binary_builtin_mixed(pmulh_h1_i32x2, int32x2_t, int32x2_t, int16x4_t, __builtin_riscv_pmulh_h1_i32x2)
+__packed_binary_builtin_mixed(pmulhsu_h0_i32x2, int32x2_t, int32x2_t, uint16x4_t, __builtin_riscv_pmulhsu_h0_i32x2)
+__packed_binary_builtin_mixed(pmulhsu_h1_i32x2, int32x2_t, int32x2_t, uint16x4_t, __builtin_riscv_pmulhsu_h1_i32x2)
+
/* Packed "Q-format" Multiply Parts Accumulate (32-bit) */
__packed_ternary_builtin_cast(mqacc_h00_i32, int, int16x2_t, __builtin_riscv_mqacc_h00_i32)
__packed_ternary_builtin_cast(mqacc_h01_i32, int, int16x2_t, __builtin_riscv_mqacc_h01_i32)
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index c6721dbeb5db8..0792df58dbfb4 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -137,7 +137,7 @@ uint64_t test_abs_u64(int64_t a) {
/* Packed Splat (32-bit) */
// RV32-LABEL: define dso_local i32 @test_pmv_s_u8x4(
-// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
// RV32-NEXT: [[ENTRY:.*:]]
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
@@ -145,7 +145,7 @@ uint64_t test_abs_u64(int64_t a) {
// RV32-NEXT: ret i32 [[TMP0]]
//
// RV64-LABEL: define dso_local i32 @test_pmv_s_u8x4(
-// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
// RV64-NEXT: [[ENTRY:.*:]]
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
@@ -10580,7 +10580,6 @@ uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) {
// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.mqacc.00.i32.v2i16(i32 [[RD]], <2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
// RV64-NEXT: ret i32 [[TMP2]]
//
-
int32_t test_mqacc_h00_i32(int32_t rd, int16x2_t rs1, int16x2_t rs2) {
return __riscv_mqacc_h00_i32(rd, rs1, rs2);
}
@@ -10950,6 +10949,346 @@ int64_t test_mqracc_w11_i64(int64_t rd, int32x2_t rs1, int32x2_t rs2) {
return __riscv_mqracc_w11_i64(rd, rs1, rs2);
}
+/* Packed Multiply High Parts (32-bit) */
+
+// RV32-LABEL: define dso_local i32 @test_pmulh_b0_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulh_b0_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulh_b0_i16x2(int16x2_t rs1, int8x4_t rs2) {
+ return __riscv_pmulh_b0_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulh_b1_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulh_b1_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulh_b1_i16x2(int16x2_t rs1, int8x4_t rs2) {
+ return __riscv_pmulh_b1_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulhsu_b0_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulhsu_b0_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhsu_b0_i16x2(int16x2_t rs1, uint8x4_t rs2) {
+ return __riscv_pmulhsu_b0_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulhsu_b1_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulhsu_b1_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> [[TMP0]], <4 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhsu_b1_i16x2(int16x2_t rs1, uint8x4_t rs2) {
+ return __riscv_pmulhsu_b1_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulh_h0_i32(
+// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulh_h0_i32(
+// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+int32_t test_mulh_h0_i32(int32_t rs1, int16x2_t rs2) {
+ return __riscv_mulh_h0_i32(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulh_h1_i32(
+// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulh_h1_i32(
+// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulh.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+int32_t test_mulh_h1_i32(int32_t rs1, int16x2_t rs2) {
+ return __riscv_mulh_h1_i32(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulhsu_h0_i32(
+// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulhsu_h0_i32(
+// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h0.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+int32_t test_mulhsu_h0_i32(int32_t rs1, uint16x2_t rs2) {
+ return __riscv_mulhsu_h0_i32(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_mulhsu_h1_i32(
+// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local signext i32 @test_mulhsu_h1_i32(
+// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.mulhsu.h1.i32.v2i16(i32 [[RS1]], <2 x i16> [[TMP0]])
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+int32_t test_mulhsu_h1_i32(int32_t rs1, uint16x2_t rs2) {
+ return __riscv_mulhsu_h1_i32(rs1, rs2);
+}
+
+/* Packed Multiply High Parts (64-bit) */
+
+// RV32-LABEL: define dso_local i64 @test_pmulh_b0_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulh_b0_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulh_b0_i16x4(int16x4_t rs1, int8x8_t rs2) {
+ return __riscv_pmulh_b0_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulh_b1_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulh_b1_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulh_b1_i16x4(int16x4_t rs1, int8x8_t rs2) {
+ return __riscv_pmulh_b1_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhsu_b0_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhsu_b0_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhsu_b0_i16x4(int16x4_t rs1, uint8x8_t rs2) {
+ return __riscv_pmulhsu_b0_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhsu_b1_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhsu_b1_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> [[TMP0]], <8 x i8> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhsu_b1_i16x4(int16x4_t rs1, uint8x8_t rs2) {
+ return __riscv_pmulhsu_b1_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulh_h0_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulh_h0_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulh_h0_i32x2(int32x2_t rs1, int16x4_t rs2) {
+ return __riscv_pmulh_h0_i32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulh_h1_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulh_h1_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulh_h1_i32x2(int32x2_t rs1, int16x4_t rs2) {
+ return __riscv_pmulh_h1_i32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhsu_h0_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhsu_h0_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhsu_h0_i32x2(int32x2_t rs1, uint16x4_t rs2) {
+ return __riscv_pmulhsu_h0_i32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhsu_h1_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhsu_h1_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhsu_h1_i32x2(int32x2_t rs1, uint16x4_t rs2) {
+ return __riscv_pmulhsu_h1_i32x2(rs1, rs2);
+}
+
/* Packed Element Extract */
// RV32-LABEL: define dso_local signext i8 @test_pget_i8x4_i8(
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 14e64c3c3584b..22f5b94e84918 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -4260,6 +4260,115 @@ int64_t test_mulsu_w11_i64(int32x2_t a, uint32x2_t b) {
return __riscv_mulsu_w11_i64(a, b);
}
+
+// CHECK-LABEL: test_pmulh_b0_i16x2:
+// CHECK: pmulh.h.b0
+int16x2_t test_pmulh_b0_i16x2(int16x2_t a, int8x4_t b) {
+ return __riscv_pmulh_b0_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulh_b1_i16x2:
+// CHECK: pmulh.h.b1
+int16x2_t test_pmulh_b1_i16x2(int16x2_t a, int8x4_t b) {
+ return __riscv_pmulh_b1_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_b0_i16x2:
+// CHECK: pmulhsu.h.b0
+int16x2_t test_pmulhsu_b0_i16x2(int16x2_t a, uint8x4_t b) {
+ return __riscv_pmulhsu_b0_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_b1_i16x2:
+// CHECK: pmulhsu.h.b1
+int16x2_t test_pmulhsu_b1_i16x2(int16x2_t a, uint8x4_t b) {
+ return __riscv_pmulhsu_b1_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_mulh_h0_i32:
+// RV32: mulh.h0
+// RV64: pmulh.w.h0
+int32_t test_mulh_h0_i32(int32_t a, int16x2_t b) {
+ return __riscv_mulh_h0_i32(a, b);
+}
+
+// CHECK-LABEL: test_mulh_h1_i32:
+// RV32: mulh.h1
+// RV64: pmulh.w.h1
+int32_t test_mulh_h1_i32(int32_t a, int16x2_t b) {
+ return __riscv_mulh_h1_i32(a, b);
+}
+
+// CHECK-LABEL: test_mulhsu_h0_i32:
+// RV32: mulhsu.h0
+// RV64: pmulhsu.w.h0
+int32_t test_mulhsu_h0_i32(int32_t a, uint16x2_t b) {
+ return __riscv_mulhsu_h0_i32(a, b);
+}
+
+// CHECK-LABEL: test_mulhsu_h1_i32:
+// RV32: mulhsu.h1
+// RV64: pmulhsu.w.h1
+int32_t test_mulhsu_h1_i32(int32_t a, uint16x2_t b) {
+ return __riscv_mulhsu_h1_i32(a, b);
+}
+
+// CHECK-LABEL: test_pmulh_b0_i16x4:
+// RV32-COUNT-2: pmulh.h.b0
+// RV64: pmulh.h.b0
+int16x4_t test_pmulh_b0_i16x4(int16x4_t a, int8x8_t b) {
+ return __riscv_pmulh_b0_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulh_b1_i16x4:
+// RV32-COUNT-2: pmulh.h.b1
+// RV64: pmulh.h.b1
+int16x4_t test_pmulh_b1_i16x4(int16x4_t a, int8x8_t b) {
+ return __riscv_pmulh_b1_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_b0_i16x4:
+// RV32-COUNT-2: pmulhsu.h.b0
+// RV64: pmulhsu.h.b0
+int16x4_t test_pmulhsu_b0_i16x4(int16x4_t a, uint8x8_t b) {
+ return __riscv_pmulhsu_b0_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_b1_i16x4:
+// RV32-COUNT-2: pmulhsu.h.b1
+// RV64: pmulhsu.h.b1
+int16x4_t test_pmulhsu_b1_i16x4(int16x4_t a, uint8x8_t b) {
+ return __riscv_pmulhsu_b1_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulh_h0_i32x2:
+// RV32-COUNT-2: mulh.h0
+// RV64: pmulh.w.h0
+int32x2_t test_pmulh_h0_i32x2(int32x2_t a, int16x4_t b) {
+ return __riscv_pmulh_h0_i32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulh_h1_i32x2:
+// RV32-COUNT-2: mulh.h1
+// RV64: pmulh.w.h1
+int32x2_t test_pmulh_h1_i32x2(int32x2_t a, int16x4_t b) {
+ return __riscv_pmulh_h1_i32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_h0_i32x2:
+// RV32-COUNT-2: mulhsu.h0
+// RV64: pmulhsu.w.h0
+int32x2_t test_pmulhsu_h0_i32x2(int32x2_t a, uint16x4_t b) {
+ return __riscv_pmulhsu_h0_i32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_h1_i32x2:
+// RV32-COUNT-2: mulhsu.h1
+// RV64: pmulhsu.w.h1
+int32x2_t test_pmulhsu_h1_i32x2(int32x2_t a, uint16x4_t b) {
+ return __riscv_pmulhsu_h1_i32x2(a, b);
+}
+
// CHECK-LABEL: test_pget_i8x4_i8:
// CHECK: srai
int8_t test_pget_i8x4_i8(int8x4_t v) { return __riscv_pget_i8x4_i8(v, 3); }
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 09399b0ea3f36..8e2d683b0af69 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2126,6 +2126,34 @@ class RVPBinaryIntrinsic
def int_riscv_pmhaccsu : RVPTernaryIntrinsic;
def int_riscv_pmhraccsu : RVPTernaryIntrinsic;
+ // Packed Multiply High Parts. The packed forms multiply the full-width
+ // element of rs1 by one byte (b0/b1) or one halfword (h0/h1) of each
+ // element of rs2, so rs2's elements are half the size of the result's.
+ class RVPMulHighPartsIntrinsic
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>,
+ LLVMSubdivide2VectorType<0>],
+ [IntrNoMem, IntrSpeculatable]>;
+ def int_riscv_pmulh_b0 : RVPMulHighPartsIntrinsic;
+ def int_riscv_pmulh_b1 : RVPMulHighPartsIntrinsic;
+ def int_riscv_pmulhsu_b0 : RVPMulHighPartsIntrinsic;
+ def int_riscv_pmulhsu_b1 : RVPMulHighPartsIntrinsic;
+ def int_riscv_pmulh_h0 : RVPMulHighPartsIntrinsic;
+ def int_riscv_pmulh_h1 : RVPMulHighPartsIntrinsic;
+ def int_riscv_pmulhsu_h0 : RVPMulHighPartsIntrinsic;
+ def int_riscv_pmulhsu_h1 : RVPMulHighPartsIntrinsic;
+
+ // The scalar forms keep a single product of the full-width rs1 and one
+ // halfword of rs2: <2 x i16> pairs with i32.
+ class RVPScalarMulHighPartsIntrinsic
+ : DefaultAttrsIntrinsic<[llvm_anyint_ty],
+ [LLVMMatchType<0>, llvm_anyvector_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+ def int_riscv_mulh_h0 : RVPScalarMulHighPartsIntrinsic;
+ def int_riscv_mulh_h1 : RVPScalarMulHighPartsIntrinsic;
+ def int_riscv_mulhsu_h0 : RVPScalarMulHighPartsIntrinsic;
+ def int_riscv_mulhsu_h1 : RVPScalarMulHighPartsIntrinsic;
+
// Packed Multiplication with Horizontal Addition.
class RVPHorizontalMulIntrinsic
: DefaultAttrsIntrinsic<[llvm_any_ty],
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 69d813fbce12d..3eb42f75541ab 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12369,6 +12369,84 @@ static unsigned getRVPMulHighAccumulateOpcode(unsigned IntNo) {
}
}
+/// Return the multiply-high-parts node for a multiply-high-parts intrinsic.
+/// The scalar spelling maps to the same node; its product is the first
+/// element.
+static unsigned getRVPMulHighPartsOpcode(unsigned IntNo) {
+ switch (IntNo) {
+ default:
+ llvm_unreachable("Unexpected RISC-V multiply-high-parts intrinsic");
+ case Intrinsic::riscv_pmulh_b0:
+ return RISCVISD::PMULH_H_B0;
+ case Intrinsic::riscv_pmulh_b1:
+ return RISCVISD::PMULH_H_B1;
+ case Intrinsic::riscv_pmulhsu_b0:
+ return RISCVISD::PMULHSU_H_B0;
+ case Intrinsic::riscv_pmulhsu_b1:
+ return RISCVISD::PMULHSU_H_B1;
+ }
+}
+
+/// Return the word multiply-high-parts node for a word multiply-high-parts
+/// intrinsic. The scalar spelling maps to the same node; its product is the
+/// first element.
+static unsigned getRVPMulHighPartsWOpcode(unsigned IntNo) {
+ switch (IntNo) {
+ default:
+ llvm_unreachable("Unexpected RISC-V word multiply-high-parts intrinsic");
+ case Intrinsic::riscv_pmulh_h0:
+ case Intrinsic::riscv_mulh_h0:
+ return RISCVISD::PMULH_W_H0;
+ case Intrinsic::riscv_pmulh_h1:
+ case Intrinsic::riscv_mulh_h1:
+ return RISCVISD::PMULH_W_H1;
+ case Intrinsic::riscv_pmulhsu_h0:
+ case Intrinsic::riscv_mulhsu_h0:
+ return RISCVISD::PMULHSU_W_H0;
+ case Intrinsic::riscv_pmulhsu_h1:
+ case Intrinsic::riscv_mulhsu_h1:
+ return RISCVISD::PMULHSU_W_H1;
+ }
+}
+
+/// Return the scalar multiply-high-parts intrinsic computing the first
+/// product of packed intrinsic \p IntNo.
+static Intrinsic::ID getRVPScalarMulHighPartsIntrinsic(unsigned IntNo) {
+ switch (IntNo) {
+ default:
+ llvm_unreachable("Unexpected RISC-V packed multiply-high-parts intrinsic");
+ case Intrinsic::riscv_pmulh_b0:
+ case Intrinsic::riscv_pmulh_h0:
+ return Intrinsic::riscv_mulh_h0;
+ case Intrinsic::riscv_pmulh_b1:
+ case Intrinsic::riscv_pmulh_h1:
+ return Intrinsic::riscv_mulh_h1;
+ case Intrinsic::riscv_pmulhsu_b0:
+ case Intrinsic::riscv_pmulhsu_h0:
+ return Intrinsic::riscv_mulhsu_h0;
+ case Intrinsic::riscv_pmulhsu_b1:
+ case Intrinsic::riscv_pmulhsu_h1:
+ return Intrinsic::riscv_mulhsu_h1;
+ }
+}
+
+/// Return the scalar halfword multiply-high-parts node for \p IntNo (RV32
+/// mulh.h0/h1).
+static unsigned getRVPScalarMulHighPartsOpcode(unsigned IntNo) {
+ switch (IntNo) {
+ default:
+ llvm_unreachable("Unexpected RISC-V scalar multiply-high-parts intrinsic");
+ case Intrinsic::riscv_mulh_h0:
+ return RISCVISD::MULH_H0;
+ case Intrinsic::riscv_mulh_h1:
+ return RISCVISD::MULH_H1;
+ case Intrinsic::riscv_mulhsu_h0:
+ return RISCVISD::MULHSU_H0;
+ case Intrinsic::riscv_mulhsu_h1:
+ return RISCVISD::MULHSU_H1;
+ }
+}
+
static unsigned getRVPQFormatAccScalarOpcode(Intrinsic::ID IntNo) {
switch (IntNo) {
default:
@@ -13211,6 +13289,77 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(MulOpc, DL, VT, Rd, Rs1, Rs2);
}
+ case Intrinsic::riscv_pmulh_b0:
+ case Intrinsic::riscv_pmulh_b1:
+ case Intrinsic::riscv_pmulhsu_b0:
+ case Intrinsic::riscv_pmulhsu_b1: {
+ EVT VT = Op.getValueType();
+ SDValue Rs1 = Op.getOperand(1);
+ SDValue Rs2 = Op.getOperand(2);
+ unsigned Opc = getRVPMulHighPartsOpcode(IntNo);
+
+ // RV32 has no single instruction for a 64-bit packed multiply-high parts.
+ // Split v4i16 into two v2i16 packed operations.
+ if (!Subtarget.is64Bit() && VT == MVT::v4i16) {
+ auto [Rs1Lo, Rs1Hi] = DAG.SplitVector(Rs1, DL);
+ auto [Rs2Lo, Rs2Hi] = DAG.SplitVector(Rs2, DL);
+ SDValue Lo = DAG.getNode(Opc, DL, MVT::v2i16, Rs1Lo, Rs2Lo);
+ SDValue Hi = DAG.getNode(Opc, DL, MVT::v2i16, Rs1Hi, Rs2Hi);
+ return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
+ }
+
+ return DAG.getNode(Opc, DL, VT, Rs1, Rs2);
+ }
+ case Intrinsic::riscv_pmulh_h0:
+ case Intrinsic::riscv_pmulh_h1:
+ case Intrinsic::riscv_pmulhsu_h0:
+ case Intrinsic::riscv_pmulhsu_h1: {
+ EVT VT = Op.getValueType();
+ SDValue Rs1 = Op.getOperand(1);
+ SDValue Rs2 = Op.getOperand(2);
+ unsigned Opc = getRVPMulHighPartsWOpcode(IntNo);
+
+ // RV32 has no single instruction for a 64-bit packed word multiply-high
+ // parts. Split v2i32 into two scalar i32 operations described by the
+ // scalar intrinsic so isel can use MULH_H0/H1.
+ if (!Subtarget.is64Bit() && VT == MVT::v2i32) {
+ auto Extract = [&](SDValue V, unsigned Idx) {
+ return DAG.getExtractVectorElt(DL, MVT::i32, V, Idx);
+ };
+ auto [Rs2Lo, Rs2Hi] = DAG.SplitVector(Rs2, DL);
+ auto ToPair = [&](SDValue V) {
+ return DAG.getBitcast(XLenVT, V);
+ };
+ SDValue Id = DAG.getTargetConstant(
+ getRVPScalarMulHighPartsIntrinsic(IntNo), DL, MVT::i32);
+ SDValue Lo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, Id,
+ Extract(Rs1, 0), ToPair(Rs2Lo));
+ SDValue Hi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, Id,
+ Extract(Rs1, 1), ToPair(Rs2Hi));
+ return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi);
+ }
+
+ if (Subtarget.is64Bit())
+ return DAG.getNode(Opc, DL, VT, Rs1, Rs2);
+
+ return SDValue();
+ }
+ case Intrinsic::riscv_mulh_h0:
+ case Intrinsic::riscv_mulh_h1:
+ case Intrinsic::riscv_mulhsu_h0:
+ case Intrinsic::riscv_mulhsu_h1: {
+ // mulh.h0/h1 exist only on RV32 and pmulh.w.h0/h1 only on RV64; the
+ // other XLEN lowers the scalar intrinsic via the packed form in
+ // ReplaceNodeResults.
+ EVT VT = Op.getValueType();
+ if (VT != MVT::i32 || Subtarget.is64Bit())
+ return SDValue();
+
+ SDValue Rs1 = Op.getOperand(1);
+ SDValue Rs2 = DAG.getBitcast(XLenVT, Op.getOperand(2));
+ unsigned Opc = getRVPScalarMulHighPartsOpcode(IntNo);
+ return DAG.getNode(Opc, DL, VT, Rs1, Rs2);
+ }
case Intrinsic::riscv_pm4add:
case Intrinsic::riscv_pm2add:
case Intrinsic::riscv_pm2add_x:
@@ -17456,6 +17605,50 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
}
reportFatalUsageError("unsupported llvm.riscv multiply-parts intrinsic");
}
+ case Intrinsic::riscv_pmulh_b0:
+ case Intrinsic::riscv_pmulh_b1:
+ case Intrinsic::riscv_pmulhsu_b0:
+ case Intrinsic::riscv_pmulhsu_b1: {
+ // A 32-bit result has no legal container on RV64; widen the result and
+ // both sources to the 64-bit packed form.
+ EVT VT = N->getValueType(0);
+ if (!Subtarget.is64Bit() || VT != MVT::v2i16)
+ return;
+
+ SDValue Undef = DAG.getUNDEF(VT);
+ SDValue Rs1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16,
+ N->getOperand(1), Undef);
+ SDValue Src2 = N->getOperand(2);
+ SDValue Rs2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i8,
+ Src2, DAG.getUNDEF(Src2.getValueType()));
+ SDValue Res = DAG.getNode(getRVPMulHighPartsOpcode(IntNo), DL, MVT::v4i16,
+ Rs1, Rs2);
+ Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0));
+ return;
+ }
+ case Intrinsic::riscv_mulh_h0:
+ case Intrinsic::riscv_mulh_h1:
+ case Intrinsic::riscv_mulhsu_h0:
+ case Intrinsic::riscv_mulhsu_h1: {
+ // mulh.h0/h1 exist only on RV32 and pmulh.w.h0/h1 only on RV64; the
+ // other XLEN has to build the product here.
+ MVT VT = N->getSimpleValueType(0);
+ MVT SrcVT = N->getOperand(2).getSimpleValueType();
+ if (Subtarget.hasStdExtP() && Subtarget.is64Bit() && VT == MVT::i32 &&
+ SrcVT == MVT::v2i16) {
+ // The halfword product is the first element of the packed one.
+ SDValue Rd = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2i32,
+ N->getOperand(1));
+ SDValue Undef = DAG.getUNDEF(SrcVT);
+ SDValue Rs1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16,
+ N->getOperand(2), Undef);
+ SDValue Res = DAG.getNode(getRVPMulHighPartsWOpcode(IntNo), DL,
+ MVT::v2i32, Rd, Rs1);
+ Results.push_back(DAG.getExtractVectorElt(DL, MVT::i32, Res, 0));
+ return;
+ }
+ reportFatalUsageError("unsupported llvm.riscv multiply-high-parts intrinsic");
+ }
case Intrinsic::riscv_macc_00:
case Intrinsic::riscv_macc_01:
case Intrinsic::riscv_macc_11:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 831a591cf6283..51d38f52b8995 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1895,6 +1895,29 @@ def riscv_pmulsu_halves_00
def riscv_pmulsu_halves_11
: RVSDNode<"PMULSU_HALVES_11", SDT_RISCVPackedWideningMulByHalves>;
+// Multiply high parts
+def SDT_RISCVMulHighParts
+ : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisVT<1, XLenVT>,
+ SDTCisVT<2, XLenVT>]>;
+def riscv_mulh_h0 : RVSDNode<"MULH_H0", SDT_RISCVMulHighParts>;
+def riscv_mulh_h1 : RVSDNode<"MULH_H1", SDT_RISCVMulHighParts>;
+def riscv_mulhsu_h0 : RVSDNode<"MULHSU_H0", SDT_RISCVMulHighParts>;
+def riscv_mulhsu_h1 : RVSDNode<"MULHSU_H1", SDT_RISCVMulHighParts>;
+
+def SDT_RISCVPackedMulHighParts
+ : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
+ SDTCisOpSmallerThanOp<2, 0>,
+ SDTCisSameSizeAs<0, 2>]>;
+def riscv_pmulh_h_b0 : RVSDNode<"PMULH_H_B0", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulh_h_b1 : RVSDNode<"PMULH_H_B1", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulhsu_h_b0 : RVSDNode<"PMULHSU_H_B0", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulhsu_h_b1 : RVSDNode<"PMULHSU_H_B1", SDT_RISCVPackedMulHighParts>;
+
+def riscv_pmulh_w_h0 : RVSDNode<"PMULH_W_H0", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulh_w_h1 : RVSDNode<"PMULH_W_H1", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulhsu_w_h0 : RVSDNode<"PMULHSU_W_H0", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulhsu_w_h1 : RVSDNode<"PMULHSU_W_H1", SDT_RISCVPackedMulHighParts>;
+
// Packed multiplication with widening horizontal addition.
def SDT_RISCVPackedWideningHorizontalAdd
: SDTypeProfile<1, 2, [SDTCisVT<0, v2i32>, SDTCisVT<1, v2i16>,
@@ -2420,6 +2443,20 @@ let Predicates = [HasStdExtP] in {
(XLenVecI8VT GPR:$rs2))),
(PMULSU_H_B11 GPR:$rs1, GPR:$rs2)>;
+ // Packed byte multiply-high parts patterns.
+ def : Pat<(XLenVecI16VT (riscv_pmulh_h_b0 (XLenVecI16VT GPR:$rs1),
+ (XLenVecI8VT GPR:$rs2))),
+ (PMULH_H_B0 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVecI16VT (riscv_pmulh_h_b1 (XLenVecI16VT GPR:$rs1),
+ (XLenVecI8VT GPR:$rs2))),
+ (PMULH_H_B1 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVecI16VT (riscv_pmulhsu_h_b0 (XLenVecI16VT GPR:$rs1),
+ (XLenVecI8VT GPR:$rs2))),
+ (PMULHSU_H_B0 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(XLenVecI16VT (riscv_pmulhsu_h_b1 (XLenVecI16VT GPR:$rs1),
+ (XLenVecI8VT GPR:$rs2))),
+ (PMULHSU_H_B1 GPR:$rs1, GPR:$rs2)>;
+
let append Predicates = [IsRV32] in {
// Scalar halfword multiply-parts accumulate patterns.
def : PatMulPartsAcc<riscv_pmacc_halves_00, MACC_H00, i32, v2i16>;
@@ -2441,6 +2478,17 @@ let append Predicates = [IsRV32] in {
def : PatMulParts<int_riscv_mulsu_00, MULSU_H00, i32, v2i16>;
def : PatMulParts<int_riscv_mulsu_11, MULSU_H11, i32, v2i16>;
+ // Scalar halfword multiply-high parts patterns. Both operands are plain
+ // GPR scalars; rs2's halfword pair is reinterpreted as a scalar.
+ def : Pat<(i32 (riscv_mulh_h0 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ (MULH_H0 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(i32 (riscv_mulh_h1 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ (MULH_H1 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(i32 (riscv_mulhsu_h0 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ (MULHSU_H0 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(i32 (riscv_mulhsu_h1 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ (MULHSU_H1 GPR:$rs1, GPR:$rs2)>;
+
def : PatGpr<bitreverse, REV_RV32>;
def : Pat<(XLenVT (riscv_sati GPR:$rs1, timm:$imm)),
@@ -3166,6 +3214,16 @@ let append Predicates = [IsRV64] in {
def : PatMulParts<int_riscv_mulsu_00, MULSU_W00, i64, v2i32>;
def : PatMulParts<int_riscv_mulsu_11, MULSU_W11, i64, v2i32>;
+ // Packed word multiply-high parts patterns.
+ def : Pat<(v2i32 (riscv_pmulh_w_h0 (v2i32 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMULH_W_H0 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmulh_w_h1 (v2i32 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMULH_W_H1 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmulhsu_w_h0 (v2i32 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMULHSU_W_H0 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v2i32 (riscv_pmulhsu_w_h1 (v2i32 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PMULHSU_W_H1 GPR:$rs1, GPR:$rs2)>;
+
// 32-bit multiply high patterns
def : PatGprGpr<mulhs, PMULH_W, v2i32>;
def : PatGprGpr<mulhu, PMULHU_W, v2i32>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index e9e04eb6b5ebe..af06335875e65 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -3827,3 +3827,96 @@ define i32 @test_maccsu_h11_i32(i32 %rd, <2 x i16> %a, <2 x i16> %b) {
%r = call i32 @llvm.riscv.maccsu.11.i32.v2i16(i32 %rd, <2 x i16> %a, <2 x i16> %b)
ret i32 %r
}
+
+; Packed Multiply High Parts.
+define <2 x i16> @test_pmulh_b0_v2i16(<2 x i16> %a, <4 x i8> %b) {
+; CHECK-LABEL: test_pmulh_b0_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulh.h.b0 a0, a0, a1
+; CHECK-NEXT: ret
+ %r = call <2 x i16> @llvm.riscv.pmulh.b0.v2i16(<2 x i16> %a, <4 x i8> %b)
+ ret <2 x i16> %r
+}
+
+define <2 x i16> @test_pmulh_b1_v2i16(<2 x i16> %a, <4 x i8> %b) {
+; CHECK-LABEL: test_pmulh_b1_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulh.h.b1 a0, a0, a1
+; CHECK-NEXT: ret
+ %r = call <2 x i16> @llvm.riscv.pmulh.b1.v2i16(<2 x i16> %a, <4 x i8> %b)
+ ret <2 x i16> %r
+}
+
+define <2 x i16> @test_pmulhsu_b0_v2i16(<2 x i16> %a, <4 x i8> %b) {
+; CHECK-LABEL: test_pmulhsu_b0_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulhsu.h.b0 a0, a0, a1
+; CHECK-NEXT: ret
+ %r = call <2 x i16> @llvm.riscv.pmulhsu.b0.v2i16(<2 x i16> %a, <4 x i8> %b)
+ ret <2 x i16> %r
+}
+
+define <2 x i16> @test_pmulhsu_b1_v2i16(<2 x i16> %a, <4 x i8> %b) {
+; CHECK-LABEL: test_pmulhsu_b1_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulhsu.h.b1 a0, a0, a1
+; CHECK-NEXT: ret
+ %r = call <2 x i16> @llvm.riscv.pmulhsu.b1.v2i16(<2 x i16> %a, <4 x i8> %b)
+ ret <2 x i16> %r
+}
+
+define i32 @test_mulh_h0_i32(i32 %a, <2 x i16> %b) {
+; RV32-LABEL: test_mulh_h0_i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulh.h0 a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_mulh_h0_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.w.h0 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call i32 @llvm.riscv.mulh.h0.i32.v2i16(i32 %a, <2 x i16> %b)
+ ret i32 %r
+}
+
+define i32 @test_mulh_h1_i32(i32 %a, <2 x i16> %b) {
+; RV32-LABEL: test_mulh_h1_i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulh.h1 a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_mulh_h1_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.w.h1 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call i32 @llvm.riscv.mulh.h1.i32.v2i16(i32 %a, <2 x i16> %b)
+ ret i32 %r
+}
+
+define i32 @test_mulhsu_h0_i32(i32 %a, <2 x i16> %b) {
+; RV32-LABEL: test_mulhsu_h0_i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhsu.h0 a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_mulhsu_h0_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.w.h0 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call i32 @llvm.riscv.mulhsu.h0.i32.v2i16(i32 %a, <2 x i16> %b)
+ ret i32 %r
+}
+
+define i32 @test_mulhsu_h1_i32(i32 %a, <2 x i16> %b) {
+; RV32-LABEL: test_mulhsu_h1_i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhsu.h1 a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_mulhsu_h1_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.w.h1 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call i32 @llvm.riscv.mulhsu.h1.i32.v2i16(i32 %a, <2 x i16> %b)
+ ret i32 %r
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 43107137fe1fa..9ac7b5ff4cf2e 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -8116,3 +8116,124 @@ define i64 @test_maccsu_w11_i64(i64 %rd, <2 x i32> %a, <2 x i32> %b) {
%r = call i64 @llvm.riscv.maccsu.11.i64.v2i32(i64 %rd, <2 x i32> %a, <2 x i32> %b)
ret i64 %r
}
+
+; Packed Multiply High Parts
+define <4 x i16> @test_pmulh_b0_v4i16(<4 x i16> %a, <8 x i8> %b) {
+; RV32-LABEL: test_pmulh_b0_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulh.h.b0 a1, a1, a3
+; RV32-NEXT: pmulh.h.b0 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulh_b0_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.h.b0 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <4 x i16> @llvm.riscv.pmulh.b0.v4i16(<4 x i16> %a, <8 x i8> %b)
+ ret <4 x i16> %r
+}
+
+define <4 x i16> @test_pmulh_b1_v4i16(<4 x i16> %a, <8 x i8> %b) {
+; RV32-LABEL: test_pmulh_b1_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulh.h.b1 a1, a1, a3
+; RV32-NEXT: pmulh.h.b1 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulh_b1_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.h.b1 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <4 x i16> @llvm.riscv.pmulh.b1.v4i16(<4 x i16> %a, <8 x i8> %b)
+ ret <4 x i16> %r
+}
+
+define <4 x i16> @test_pmulhsu_b0_v4i16(<4 x i16> %a, <8 x i8> %b) {
+; RV32-LABEL: test_pmulhsu_b0_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulhsu.h.b0 a1, a1, a3
+; RV32-NEXT: pmulhsu.h.b0 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhsu_b0_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.h.b0 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <4 x i16> @llvm.riscv.pmulhsu.b0.v4i16(<4 x i16> %a, <8 x i8> %b)
+ ret <4 x i16> %r
+}
+
+define <4 x i16> @test_pmulhsu_b1_v4i16(<4 x i16> %a, <8 x i8> %b) {
+; RV32-LABEL: test_pmulhsu_b1_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulhsu.h.b1 a1, a1, a3
+; RV32-NEXT: pmulhsu.h.b1 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhsu_b1_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.h.b1 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <4 x i16> @llvm.riscv.pmulhsu.b1.v4i16(<4 x i16> %a, <8 x i8> %b)
+ ret <4 x i16> %r
+}
+
+define <2 x i32> @test_pmulh_h0_v2i32(<2 x i32> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulh_h0_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulh.h0 a1, a1, a3
+; RV32-NEXT: mulh.h0 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulh_h0_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.w.h0 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <2 x i32> @llvm.riscv.pmulh.h0.v2i32(<2 x i32> %a, <4 x i16> %b)
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @test_pmulh_h1_v2i32(<2 x i32> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulh_h1_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulh.h1 a1, a1, a3
+; RV32-NEXT: mulh.h1 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulh_h1_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.w.h1 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <2 x i32> @llvm.riscv.pmulh.h1.v2i32(<2 x i32> %a, <4 x i16> %b)
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @test_pmulhsu_h0_v2i32(<2 x i32> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulhsu_h0_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhsu.h0 a1, a1, a3
+; RV32-NEXT: mulhsu.h0 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhsu_h0_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.w.h0 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <2 x i32> @llvm.riscv.pmulhsu.h0.v2i32(<2 x i32> %a, <4 x i16> %b)
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @test_pmulhsu_h1_v2i32(<2 x i32> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulhsu_h1_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhsu.h1 a1, a1, a3
+; RV32-NEXT: mulhsu.h1 a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhsu_h1_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.w.h1 a0, a0, a1
+; RV64-NEXT: ret
+ %r = call <2 x i32> @llvm.riscv.pmulhsu.h1.v2i32(<2 x i32> %a, <4 x i16> %b)
+ ret <2 x i32> %r
+}
>From 62832b3661205935ed9e15cb6bae94da945d953c Mon Sep 17 00:00:00 2001
From: Dongyan Chen <chendongyan at isrc.iscas.ac.cn>
Date: Tue, 22 Sep 2026 02:24:57 +0000
Subject: [PATCH 2/3] Simplify multiply high parts node types and lowering
Address review feedback on the multiply-high-parts intrinsics
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 45 +++++----------------
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 38 ++++++++---------
2 files changed, 28 insertions(+), 55 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 3eb42f75541ab..431f85648ef35 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12409,39 +12409,23 @@ static unsigned getRVPMulHighPartsWOpcode(unsigned IntNo) {
}
}
-/// Return the scalar multiply-high-parts intrinsic computing the first
-/// product of packed intrinsic \p IntNo.
-static Intrinsic::ID getRVPScalarMulHighPartsIntrinsic(unsigned IntNo) {
- switch (IntNo) {
- default:
- llvm_unreachable("Unexpected RISC-V packed multiply-high-parts intrinsic");
- case Intrinsic::riscv_pmulh_b0:
- case Intrinsic::riscv_pmulh_h0:
- return Intrinsic::riscv_mulh_h0;
- case Intrinsic::riscv_pmulh_b1:
- case Intrinsic::riscv_pmulh_h1:
- return Intrinsic::riscv_mulh_h1;
- case Intrinsic::riscv_pmulhsu_b0:
- case Intrinsic::riscv_pmulhsu_h0:
- return Intrinsic::riscv_mulhsu_h0;
- case Intrinsic::riscv_pmulhsu_b1:
- case Intrinsic::riscv_pmulhsu_h1:
- return Intrinsic::riscv_mulhsu_h1;
- }
-}
-
/// Return the scalar halfword multiply-high-parts node for \p IntNo (RV32
-/// mulh.h0/h1).
+/// mulh.h0/h1). The packed word spelling maps to the same node; its product
+/// is the first element.
static unsigned getRVPScalarMulHighPartsOpcode(unsigned IntNo) {
switch (IntNo) {
default:
llvm_unreachable("Unexpected RISC-V scalar multiply-high-parts intrinsic");
+ case Intrinsic::riscv_pmulh_h0:
case Intrinsic::riscv_mulh_h0:
return RISCVISD::MULH_H0;
+ case Intrinsic::riscv_pmulh_h1:
case Intrinsic::riscv_mulh_h1:
return RISCVISD::MULH_H1;
+ case Intrinsic::riscv_pmulhsu_h0:
case Intrinsic::riscv_mulhsu_h0:
return RISCVISD::MULHSU_H0;
+ case Intrinsic::riscv_pmulhsu_h1:
case Intrinsic::riscv_mulhsu_h1:
return RISCVISD::MULHSU_H1;
}
@@ -13320,22 +13304,15 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
unsigned Opc = getRVPMulHighPartsWOpcode(IntNo);
// RV32 has no single instruction for a 64-bit packed word multiply-high
- // parts. Split v2i32 into two scalar i32 operations described by the
- // scalar intrinsic so isel can use MULH_H0/H1.
+ // parts. Split v2i32 into two scalar operations, one per result word.
if (!Subtarget.is64Bit() && VT == MVT::v2i32) {
auto Extract = [&](SDValue V, unsigned Idx) {
return DAG.getExtractVectorElt(DL, MVT::i32, V, Idx);
};
auto [Rs2Lo, Rs2Hi] = DAG.SplitVector(Rs2, DL);
- auto ToPair = [&](SDValue V) {
- return DAG.getBitcast(XLenVT, V);
- };
- SDValue Id = DAG.getTargetConstant(
- getRVPScalarMulHighPartsIntrinsic(IntNo), DL, MVT::i32);
- SDValue Lo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, Id,
- Extract(Rs1, 0), ToPair(Rs2Lo));
- SDValue Hi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, Id,
- Extract(Rs1, 1), ToPair(Rs2Hi));
+ unsigned SOpc = getRVPScalarMulHighPartsOpcode(IntNo);
+ SDValue Lo = DAG.getNode(SOpc, DL, MVT::i32, Extract(Rs1, 0), Rs2Lo);
+ SDValue Hi = DAG.getNode(SOpc, DL, MVT::i32, Extract(Rs1, 1), Rs2Hi);
return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi);
}
@@ -13356,7 +13333,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return SDValue();
SDValue Rs1 = Op.getOperand(1);
- SDValue Rs2 = DAG.getBitcast(XLenVT, Op.getOperand(2));
+ SDValue Rs2 = Op.getOperand(2);
unsigned Opc = getRVPScalarMulHighPartsOpcode(IntNo);
return DAG.getNode(Opc, DL, VT, Rs1, Rs2);
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 51d38f52b8995..24096ab7d4a50 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1895,28 +1895,25 @@ def riscv_pmulsu_halves_00
def riscv_pmulsu_halves_11
: RVSDNode<"PMULSU_HALVES_11", SDT_RISCVPackedWideningMulByHalves>;
-// Multiply high parts
+// Multiply high parts. The result and rs1 keep the full element width; rs2
+// is the vector of half-width elements selecting the part to multiply. The
+// scalar form keeps a single product (RV32 mulh.h0/h1).
def SDT_RISCVMulHighParts
- : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisVT<1, XLenVT>,
- SDTCisVT<2, XLenVT>]>;
+ : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<2>]>;
def riscv_mulh_h0 : RVSDNode<"MULH_H0", SDT_RISCVMulHighParts>;
def riscv_mulh_h1 : RVSDNode<"MULH_H1", SDT_RISCVMulHighParts>;
def riscv_mulhsu_h0 : RVSDNode<"MULHSU_H0", SDT_RISCVMulHighParts>;
def riscv_mulhsu_h1 : RVSDNode<"MULHSU_H1", SDT_RISCVMulHighParts>;
-def SDT_RISCVPackedMulHighParts
- : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
- SDTCisOpSmallerThanOp<2, 0>,
- SDTCisSameSizeAs<0, 2>]>;
-def riscv_pmulh_h_b0 : RVSDNode<"PMULH_H_B0", SDT_RISCVPackedMulHighParts>;
-def riscv_pmulh_h_b1 : RVSDNode<"PMULH_H_B1", SDT_RISCVPackedMulHighParts>;
-def riscv_pmulhsu_h_b0 : RVSDNode<"PMULHSU_H_B0", SDT_RISCVPackedMulHighParts>;
-def riscv_pmulhsu_h_b1 : RVSDNode<"PMULHSU_H_B1", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulh_h_b0 : RVSDNode<"PMULH_H_B0", SDT_RISCVMulHighParts>;
+def riscv_pmulh_h_b1 : RVSDNode<"PMULH_H_B1", SDT_RISCVMulHighParts>;
+def riscv_pmulhsu_h_b0 : RVSDNode<"PMULHSU_H_B0", SDT_RISCVMulHighParts>;
+def riscv_pmulhsu_h_b1 : RVSDNode<"PMULHSU_H_B1", SDT_RISCVMulHighParts>;
-def riscv_pmulh_w_h0 : RVSDNode<"PMULH_W_H0", SDT_RISCVPackedMulHighParts>;
-def riscv_pmulh_w_h1 : RVSDNode<"PMULH_W_H1", SDT_RISCVPackedMulHighParts>;
-def riscv_pmulhsu_w_h0 : RVSDNode<"PMULHSU_W_H0", SDT_RISCVPackedMulHighParts>;
-def riscv_pmulhsu_w_h1 : RVSDNode<"PMULHSU_W_H1", SDT_RISCVPackedMulHighParts>;
+def riscv_pmulh_w_h0 : RVSDNode<"PMULH_W_H0", SDT_RISCVMulHighParts>;
+def riscv_pmulh_w_h1 : RVSDNode<"PMULH_W_H1", SDT_RISCVMulHighParts>;
+def riscv_pmulhsu_w_h0 : RVSDNode<"PMULHSU_W_H0", SDT_RISCVMulHighParts>;
+def riscv_pmulhsu_w_h1 : RVSDNode<"PMULHSU_W_H1", SDT_RISCVMulHighParts>;
// Packed multiplication with widening horizontal addition.
def SDT_RISCVPackedWideningHorizontalAdd
@@ -2478,15 +2475,14 @@ let append Predicates = [IsRV32] in {
def : PatMulParts<int_riscv_mulsu_00, MULSU_H00, i32, v2i16>;
def : PatMulParts<int_riscv_mulsu_11, MULSU_H11, i32, v2i16>;
- // Scalar halfword multiply-high parts patterns. Both operands are plain
- // GPR scalars; rs2's halfword pair is reinterpreted as a scalar.
- def : Pat<(i32 (riscv_mulh_h0 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ // Scalar halfword multiply-high parts patterns.
+ def : Pat<(i32 (riscv_mulh_h0 (i32 GPR:$rs1), (v2i16 GPR:$rs2))),
(MULH_H0 GPR:$rs1, GPR:$rs2)>;
- def : Pat<(i32 (riscv_mulh_h1 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ def : Pat<(i32 (riscv_mulh_h1 (i32 GPR:$rs1), (v2i16 GPR:$rs2))),
(MULH_H1 GPR:$rs1, GPR:$rs2)>;
- def : Pat<(i32 (riscv_mulhsu_h0 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ def : Pat<(i32 (riscv_mulhsu_h0 (i32 GPR:$rs1), (v2i16 GPR:$rs2))),
(MULHSU_H0 GPR:$rs1, GPR:$rs2)>;
- def : Pat<(i32 (riscv_mulhsu_h1 (i32 GPR:$rs1), (i32 GPR:$rs2))),
+ def : Pat<(i32 (riscv_mulhsu_h1 (i32 GPR:$rs1), (v2i16 GPR:$rs2))),
(MULHSU_H1 GPR:$rs1, GPR:$rs2)>;
def : PatGpr<bitreverse, REV_RV32>;
>From 8c7412b01096aca1905812cb0ac6d61e55237d69 Mon Sep 17 00:00:00 2001
From: Dongyan Chen <chendongyan at isrc.iscas.ac.cn>
Date: Tue, 22 Sep 2026 08:17:43 +0000
Subject: [PATCH 3/3] [RISCV][P-ext] Fix clang-format in multiply high parts
changes
---
.../intrinsic-header-tests/riscv_packed_simd.c | 1 -
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 ++++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 22f5b94e84918..37314589eef93 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -4260,7 +4260,6 @@ int64_t test_mulsu_w11_i64(int32x2_t a, uint32x2_t b) {
return __riscv_mulsu_w11_i64(a, b);
}
-
// CHECK-LABEL: test_pmulh_b0_i16x2:
// CHECK: pmulh.h.b0
int16x2_t test_pmulh_b0_i16x2(int16x2_t a, int8x4_t b) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 431f85648ef35..bc3e4bbf31e48 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17596,8 +17596,8 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
SDValue Rs1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16,
N->getOperand(1), Undef);
SDValue Src2 = N->getOperand(2);
- SDValue Rs2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i8,
- Src2, DAG.getUNDEF(Src2.getValueType()));
+ SDValue Rs2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i8, Src2,
+ DAG.getUNDEF(Src2.getValueType()));
SDValue Res = DAG.getNode(getRVPMulHighPartsOpcode(IntNo), DL, MVT::v4i16,
Rs1, Rs2);
Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0));
@@ -17624,7 +17624,8 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(DAG.getExtractVectorElt(DL, MVT::i32, Res, 0));
return;
}
- reportFatalUsageError("unsupported llvm.riscv multiply-high-parts intrinsic");
+ reportFatalUsageError(
+ "unsupported llvm.riscv multiply-high-parts intrinsic");
}
case Intrinsic::riscv_macc_00:
case Intrinsic::riscv_macc_01:
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