[llvm] [AArch64][NeoverseV1/V2] Fix FMULX scalar latency (PR #224540)

[Julien Villette via llvm-commits]

https://github.com/jvillette38 updated https://github.com/llvm/llvm-project/pull/224540

>From cd8023ebad7be6acc417bf6b51d6ee960b327437 Mon Sep 17 00:00:00 2001
From: Julien Villette <julien.villette at sipearl.com>
Date: Thu, 17 Sep 2026 15:15:40 +0200
Subject: [PATCH] [AArch64][NeoverseV1/V2] Fix FMULX scalar latency

The "ASIMD FP multiply" InstRW regex required a "v" suffix, so the
scalar register-register forms FMULX16, FMULX32 and FMULX64 fell back
to a generic class with latency 2.

Measured on Neoverse V1 and V2 hardware with a single dependency
chain: 3 cycles, the same as the vector forms and as FMUL, matching
the SOG row.
---
 llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td           | 2 +-
 llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td           | 2 +-
 .../tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s  | 6 +++---
 .../tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s  | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index b8bab7ece3a2b..c777784007abc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -1007,7 +1007,7 @@ def : InstRW<[V1Write_4c_1V], (instregex "^FCADD(v[48]f16|v[24]f32|v2f64)$")>;
 def : InstRW<[V1Wr_FCMA, V1Rd_FCMA], (instregex "^FCMLAv")>;
 
 // ASIMD FP multiply
-def : InstRW<[V1Wr_FPM], (instregex "^FMULX?v")>;
+def : InstRW<[V1Wr_FPM], (instregex "^FMULX?v", "^FMULX(16|32|64)$")>;
 
 // ASIMD FP multiply accumulate
 def : InstRW<[V1Wr_FPMA, V1Rd_FPMA], (instregex "^FML[AS]v")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index aeca6253a0bdb..046882756cf5d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -1630,7 +1630,7 @@ def : InstRW<[V2Write_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
 def : InstRW<[V2Write_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
 
 // ASIMD FP multiply
-def : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv")>;
+def : InstRW<[V2Wr_VFM], (instregex "^FMULv", "^FMULXv", "^FMULX(16|32|64)$")>;
 
 // ASIMD FP multiply accumulate
 def : InstRW<[V2Wr_VFMA, V2Rd_VFMA], (instregex "^FMLAv", "^FMLSv")>;
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
index 64c5f3f594c69..5432b995f29a7 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
@@ -378,10 +378,10 @@
 # CHECK-NEXT:  1      3     0.25                        fmul	s0, s1, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmul	v0.2s, v0.2s, v0.2s
 # CHECK-NEXT:  1      3     0.25                        fmulx	d0, d4, v0.d[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	d23, d11, d1
-# CHECK-NEXT:  1      2     0.25                        fmulx	s20, s22, s15
+# CHECK-NEXT:  1      3     0.25                        fmulx	d23, d11, d1
+# CHECK-NEXT:  1      3     0.25                        fmulx	s20, s22, s15
 # CHECK-NEXT:  1      3     0.25                        fmulx	h18, h17, v7.h[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	h20, h25, h0
+# CHECK-NEXT:  1      3     0.25                        fmulx	h20, h25, h0
 # CHECK-NEXT:  1      3     0.25                        fmulx	s3, s5, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmulx	v0.2d, v0.2d, v0.2d
 # CHECK-NEXT:  1      3     0.25                        fmulx	v28.4h, v25.4h, v15.h[1]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
index ac25e6b79defc..0126d7d3ce47b 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
@@ -378,10 +378,10 @@
 # CHECK-NEXT:  1      3     0.25                        fmul	s0, s1, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmul	v0.2s, v0.2s, v0.2s
 # CHECK-NEXT:  1      3     0.25                        fmulx	d0, d4, v0.d[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	d23, d11, d1
-# CHECK-NEXT:  1      2     0.25                        fmulx	s20, s22, s15
+# CHECK-NEXT:  1      3     0.25                        fmulx	d23, d11, d1
+# CHECK-NEXT:  1      3     0.25                        fmulx	s20, s22, s15
 # CHECK-NEXT:  1      3     0.25                        fmulx	h18, h17, v7.h[1]
-# CHECK-NEXT:  1      2     0.25                        fmulx	h20, h25, h0
+# CHECK-NEXT:  1      3     0.25                        fmulx	h20, h25, h0
 # CHECK-NEXT:  1      3     0.25                        fmulx	s3, s5, v0.s[3]
 # CHECK-NEXT:  1      3     0.25                        fmulx	v0.2d, v0.2d, v0.2d
 # CHECK-NEXT:  1      3     0.25                        fmulx	v28.4h, v25.4h, v15.h[1]