[llvm] b65e290 - [ARM] Fix swapped condition in PerformVSetCCToVCTPCombine. (#225112)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 00:08:14 PDT 2026
Author: David Green
Date: 2026-09-22T08:08:06+01:00
New Revision: b65e29010b8e05bbb916a8c0de163c9d1bb223ec
URL: https://github.com/llvm/llvm-project/commit/b65e29010b8e05bbb916a8c0de163c9d1bb223ec
DIFF: https://github.com/llvm/llvm-project/commit/b65e29010b8e05bbb916a8c0de163c9d1bb223ec.diff
LOG: [ARM] Fix swapped condition in PerformVSetCCToVCTPCombine. (#225112)
This was swapping the wrong condition to a SETUGT. Came up in #224857.
Also remove vctp64 as we cannot fold 64bit integers to vctp.
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb2/mve-vctp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 760ae18be9487..194b597bc77ba 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13486,7 +13486,7 @@ static SDValue PerformVSetCCToVCTPCombine(SDNode *N,
!DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
return SDValue();
- if (CC == ISD::SETUGE) {
+ if (CC == ISD::SETUGT) {
std::swap(Op0, Op1);
CC = ISD::SETULT;
}
@@ -13510,9 +13510,6 @@ static SDValue PerformVSetCCToVCTPCombine(SDNode *N,
unsigned Opc;
switch (VT.getVectorNumElements()) {
- case 2:
- Opc = Intrinsic::arm_mve_vctp64;
- break;
case 4:
Opc = Intrinsic::arm_mve_vctp32;
break;
diff --git a/llvm/test/CodeGen/Thumb2/mve-vctp.ll b/llvm/test/CodeGen/Thumb2/mve-vctp.ll
index 02f7de5a07244..6763bd436f8b3 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vctp.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vctp.ll
@@ -85,8 +85,8 @@ entry:
ret <4 x i32> %s
}
-define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(i32 %n, <4 x i32> %a, <4 x i32> %b) {
-; CHECK-LABEL: vcmp_uge_v4i32:
+define arm_aapcs_vfpcc <4 x i32> @vcmp_ugt_v4i32(i32 %n, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: vcmp_ugt_v4i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vctp.32 r0
; CHECK-NEXT: vpst
@@ -96,7 +96,7 @@ define arm_aapcs_vfpcc <4 x i32> @vcmp_uge_v4i32(i32 %n, <4 x i32> %a, <4 x i32>
entry:
%i = insertelement <4 x i32> undef, i32 %n, i32 0
%ns = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
- %c = icmp uge <4 x i32> %ns, <i32 0, i32 1, i32 2, i32 3>
+ %c = icmp ugt <4 x i32> %ns, <i32 0, i32 1, i32 2, i32 3>
%s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %s
}
@@ -135,8 +135,8 @@ entry:
ret <8 x i16> %s
}
-define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(i16 %n, <8 x i16> %a, <8 x i16> %b) {
-; CHECK-LABEL: vcmp_uge_v8i16:
+define arm_aapcs_vfpcc <8 x i16> @vcmp_ugt_v8i16(i16 %n, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: vcmp_ugt_v8i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: vctp.16 r0
@@ -147,7 +147,7 @@ define arm_aapcs_vfpcc <8 x i16> @vcmp_uge_v8i16(i16 %n, <8 x i16> %a, <8 x i16>
entry:
%i = insertelement <8 x i16> undef, i16 %n, i32 0
%ns = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
- %c = icmp uge <8 x i16> %ns, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+ %c = icmp ugt <8 x i16> %ns, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
%s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %s
}
@@ -170,8 +170,8 @@ entry:
ret <16 x i8> %s
}
-define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(i8 %n, <16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: vcmp_uge_v16i8:
+define arm_aapcs_vfpcc <16 x i8> @vcmp_ugt_v16i8(i8 %n, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: vcmp_ugt_v16i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: vctp.8 r0
@@ -179,6 +179,42 @@ define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(i8 %n, <16 x i8> %a, <16 x i8>
; CHECK-NEXT: vmovt q1, q0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
+entry:
+ %i = insertelement <16 x i8> undef, i8 %n, i32 0
+ %ns = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
+ %c = icmp ugt <16 x i8> %ns, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>
+ %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
+ ret <16 x i8> %s
+}
+
+define arm_aapcs_vfpcc <16 x i8> @vcmp_uge_v16i8(i8 %n, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: vcmp_uge_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vdup.8 q2, r0
+; CHECK-NEXT: adr r0, .LCPI11_0
+; CHECK-NEXT: vldrw.u32 q3, [r0]
+; CHECK-NEXT: vcmp.u8 cs, q2, q3
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI11_0:
+; CHECK-NEXT: .byte 0 @ 0x0
+; CHECK-NEXT: .byte 1 @ 0x1
+; CHECK-NEXT: .byte 2 @ 0x2
+; CHECK-NEXT: .byte 3 @ 0x3
+; CHECK-NEXT: .byte 4 @ 0x4
+; CHECK-NEXT: .byte 5 @ 0x5
+; CHECK-NEXT: .byte 6 @ 0x6
+; CHECK-NEXT: .byte 7 @ 0x7
+; CHECK-NEXT: .byte 8 @ 0x8
+; CHECK-NEXT: .byte 9 @ 0x9
+; CHECK-NEXT: .byte 10 @ 0xa
+; CHECK-NEXT: .byte 11 @ 0xb
+; CHECK-NEXT: .byte 12 @ 0xc
+; CHECK-NEXT: .byte 13 @ 0xd
+; CHECK-NEXT: .byte 14 @ 0xe
+; CHECK-NEXT: .byte 15 @ 0xf
entry:
%i = insertelement <16 x i8> undef, i8 %n, i32 0
%ns = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -191,10 +227,17 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @vcmp_ult_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vcmp_ult_v2i64:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vctp.64 r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q1, q0
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: rsbs r3, r0, #0
+; CHECK-NEXT: mov.w r2, #0
+; CHECK-NEXT: sbcs.w r3, r2, r1
+; CHECK-NEXT: csetm r3, lo
+; CHECK-NEXT: rsbs.w r0, r0, #1
+; CHECK-NEXT: sbcs.w r0, r2, r1
+; CHECK-NEXT: bfi r2, r3, #0, #8
+; CHECK-NEXT: csetm r0, lo
+; CHECK-NEXT: bfi r2, r0, #8, #8
+; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%i = insertelement <2 x i64> undef, i64 %n, i32 0
@@ -204,24 +247,25 @@ entry:
ret <2 x i64> %s
}
-define arm_aapcs_vfpcc <2 x i64> @vcmp_uge_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) {
-; CHECK-LABEL: vcmp_uge_v2i64:
+define arm_aapcs_vfpcc <2 x i64> @vcmp_ugt_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: vcmp_ugt_v2i64:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vctp.64 r0
-; CHECK-NEXT: vpst
-; CHECK-NEXT: vmovt q1, q0
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: rsbs r3, r0, #0
+; CHECK-NEXT: mov.w r2, #0
+; CHECK-NEXT: sbcs.w r3, r2, r1
+; CHECK-NEXT: csetm r3, lo
+; CHECK-NEXT: rsbs.w r0, r0, #1
+; CHECK-NEXT: sbcs.w r0, r2, r1
+; CHECK-NEXT: bfi r2, r3, #0, #8
+; CHECK-NEXT: csetm r0, lo
+; CHECK-NEXT: bfi r2, r0, #8, #8
+; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%i = insertelement <2 x i64> undef, i64 %n, i32 0
%ns = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
- %c = icmp uge <2 x i64> %ns, <i64 0, i64 1>
+ %c = icmp ugt <2 x i64> %ns, <i64 0, i64 1>
%s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s
}
-
-
-declare <16 x i1> @llvm.arm.mve.vctp8(i32)
-declare <8 x i1> @llvm.arm.mve.vctp16(i32)
-declare <4 x i1> @llvm.arm.mve.vctp32(i32)
-declare <2 x i1> @llvm.arm.mve.vctp64(i32)
More information about the llvm-commits
mailing list