[llvm] [X86] Fold FMSUBADD into VFCMULC for fp16 complex conjugate multiply (PR #224533)
Rohan Shenoy via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 21 23:27:32 PDT 2026
https://github.com/222rohan updated https://github.com/llvm/llvm-project/pull/224533
>From 98232cc5dc94a4f7fc91651aeff730761f8c715b Mon Sep 17 00:00:00 2001
From: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: Fri, 18 Sep 2026 11:49:59 +0530
Subject: [PATCH 1/5] pre-fold
---
.../X86/avx512fp16-combine-fmsubadd.ll | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
new file mode 100644
index 0000000000000..741abc13584b7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s
+
+define <8 x half> @test_128(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: test_128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpshuflw {{.*#+}} xmm2 = xmm1[0,0,2,2,4,5,6,7]
+; CHECK-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,4,6,6]
+; CHECK-NEXT: vprold $16, %xmm0, %xmm3
+; CHECK-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[1,1,3,3,4,5,6,7]
+; CHECK-NEXT: vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,5,7,7]
+; CHECK-NEXT: vmulph %xmm1, %xmm3, %xmm1
+; CHECK-NEXT: vfmsubadd213ph %xmm1, %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %dup_even_b = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
+ %mul_re = fmul contract <8 x half> %a, %dup_even_b
+ %swap_a = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+ %dup_odd_b = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
+ %mul_im = fmul contract <8 x half> %swap_a, %dup_odd_b
+ %add = fadd contract <8 x half> %mul_re, %mul_im
+ %sub = fsub contract <8 x half> %mul_re, %mul_im
+ %cmul = shufflevector <8 x half> %add, <8 x half> %sub, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+ ret <8 x half> %cmul
+}
+
+define <16 x half> @test_256(<16 x half> %a, <16 x half> %b) {
+; CHECK-LABEL: test_256:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpshuflw {{.*#+}} ymm2 = ymm1[0,0,2,2,4,5,6,7,8,8,10,10,12,13,14,15]
+; CHECK-NEXT: vpshufhw {{.*#+}} ymm2 = ymm2[0,1,2,3,4,4,6,6,8,9,10,11,12,12,14,14]
+; CHECK-NEXT: vprold $16, %ymm0, %ymm3
+; CHECK-NEXT: vpshuflw {{.*#+}} ymm1 = ymm1[1,1,3,3,4,5,6,7,9,9,11,11,12,13,14,15]
+; CHECK-NEXT: vpshufhw {{.*#+}} ymm1 = ymm1[0,1,2,3,5,5,7,7,8,9,10,11,13,13,15,15]
+; CHECK-NEXT: vmulph %ymm3, %ymm1, %ymm1
+; CHECK-NEXT: vfmsubadd213ph %ymm1, %ymm2, %ymm0
+; CHECK-NEXT: retq
+ %dup_even_b = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
+ %mul_re = fmul contract <16 x half> %dup_even_b, %a
+ %swap_a = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
+ %dup_odd_b = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
+ %mul_im = fmul contract <16 x half> %dup_odd_b, %swap_a
+ %add = fadd contract <16 x half> %mul_re, %mul_im
+ %sub = fsub contract <16 x half> %mul_re, %mul_im
+ %cmul = shufflevector <16 x half> %add, <16 x half> %sub, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+ ret <16 x half> %cmul
+}
+
+define <32 x half> @test_512(<32 x half> %a, <32 x half> %b) {
+; CHECK-LABEL: test_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpshuflw {{.*#+}} zmm2 = zmm1[0,0,2,2,4,5,6,7,8,8,10,10,12,13,14,15,16,16,18,18,20,21,22,23,24,24,26,26,28,29,30,31]
+; CHECK-NEXT: vpshufhw {{.*#+}} zmm2 = zmm2[0,1,2,3,4,4,6,6,8,9,10,11,12,12,14,14,16,17,18,19,20,20,22,22,24,25,26,27,28,28,30,30]
+; CHECK-NEXT: vprold $16, %zmm0, %zmm3
+; CHECK-NEXT: vpshuflw {{.*#+}} zmm1 = zmm1[1,1,3,3,4,5,6,7,9,9,11,11,12,13,14,15,17,17,19,19,20,21,22,23,25,25,27,27,28,29,30,31]
+; CHECK-NEXT: vpshufhw {{.*#+}} zmm1 = zmm1[0,1,2,3,5,5,7,7,8,9,10,11,13,13,15,15,16,17,18,19,21,21,23,23,24,25,26,27,29,29,31,31]
+; CHECK-NEXT: vmulph %zmm1, %zmm3, %zmm1
+; CHECK-NEXT: vfmsubadd213ph %zmm1, %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %dup_even_b = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14, i32 16, i32 16, i32 18, i32 18, i32 20, i32 20, i32 22, i32 22, i32 24, i32 24, i32 26, i32 26, i32 28, i32 28, i32 30, i32 30>
+ %mul_re = fmul contract <32 x half> %dup_even_b, %a
+ %swap_a = shufflevector <32 x half> %a, <32 x half> poison, <32 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14, i32 17, i32 16, i32 19, i32 18, i32 21, i32 20, i32 23, i32 22, i32 25, i32 24, i32 27, i32 26, i32 29, i32 28, i32 31, i32 30>
+ %dup_odd_b = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15, i32 17, i32 17, i32 19, i32 19, i32 21, i32 21, i32 23, i32 23, i32 25, i32 25, i32 27, i32 27, i32 29, i32 29, i32 31, i32 31>
+ %mul_im = fmul contract <32 x half> %swap_a, %dup_odd_b
+ %add = fadd contract <32 x half> %mul_re, %mul_im
+ %sub = fsub contract <32 x half> %mul_re, %mul_im
+ %cmul = shufflevector <32 x half> %add, <32 x half> %sub, <32 x i32> <i32 0, i32 33, i32 2, i32 35, i32 4, i32 37, i32 6, i32 39, i32 8, i32 41, i32 10, i32 43, i32 12, i32 45, i32 14, i32 47, i32 16, i32 49, i32 18, i32 51, i32 20, i32 53, i32 22, i32 55, i32 24, i32 57, i32 26, i32 59, i32 28, i32 61, i32 30, i32 63>
+ ret <32 x half> %cmul
+}
>From 610a9e045d6cd692f0b733af88fde957b835285f Mon Sep 17 00:00:00 2001
From: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: Fri, 18 Sep 2026 11:55:29 +0530
Subject: [PATCH 2/5] post-fold
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 40 ++++++++++++-------
.../X86/avx512fp16-combine-fmsubadd.ll | 27 +++----------
2 files changed, 31 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 64a4a191e5881..e67d6fd8879e6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -56217,7 +56217,7 @@ static SDValue combineFMulcFCMulc(SDNode *N, SelectionDAG &DAG,
}
// We try to match the following pattern from FMSUBADD(X, A, M) to lower it
-// into complex conjugate fmadd for fp16 (#216290).
+// into complex conjugate multiply for fp16.
// for vector of the complex form v <v0r, v0i, v1r, v1i, ...>
// and 2 complex vectors a, b,
// X = duplicate real (b) : <b0r, b0r, b1r, b1r, ...>
@@ -56284,17 +56284,8 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
bool IsConj;
SDValue FAddOp1, MulOp0, MulOp1;
MVT CVT = MVT::getVectorVT(MVT::f32, VT.getVectorNumElements() / 2);
- auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj, &DAG,
- &IsVectorAllNegativeZero, &CVT](SDValue N) -> bool {
- if (N.getOpcode() == X86ISD::FMSUBADD && N.hasOneUse()) {
- SDValue A, B;
- if (!isCFMulFromFMSUBADD(N, DAG, A, B))
- return false;
- IsConj = true;
- MulOp0 = DAG.getBitcast(CVT, A);
- MulOp1 = DAG.getBitcast(CVT, B);
- return true;
- }
+ auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj,
+ &IsVectorAllNegativeZero](SDValue N) -> bool {
if (!N.hasOneUse() || N.getOpcode() != ISD::BITCAST)
return false;
SDValue Op0 = N.getOperand(0);
@@ -58559,18 +58550,37 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
}
}
+// Combine FMSUBADD(A, B, C) -> VFCMULC(A, B) for fp16 (complex)
// Combine FMADDSUB(A, B, FNEG(C)) -> FMSUBADD(A, B, C)
// Combine FMSUBADD(A, B, FNEG(C)) -> FMADDSUB(A, B, C)
static SDValue combineFMADDSUB(SDNode *N, SelectionDAG &DAG,
+ const X86Subtarget &Subtarget,
TargetLowering::DAGCombinerInfo &DCI) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
+ SDValue N2 = N->getOperand(2);
+
+ if (N->getOpcode() == X86ISD::FMSUBADD && Subtarget.hasFP16() &&
+ N->hasOneUse() &&
+ (VT == MVT::v8f16 || VT == MVT::v16f16 || VT == MVT::v32f16)) {
+ SDValue A, B;
+ if (isCFMulFromFMSUBADD(SDValue(N, 0), DAG, A, B)) {
+ MVT CVT = MVT::getVectorVT(MVT::f32, VT.getVectorNumElements() / 2);
+ SDValue MulOp0 = DAG.getBitcast(CVT, A);
+ SDValue MulOp1 = DAG.getBitcast(CVT, B);
+ // FMSUBADD has no flags, so we use the flags from the FMUL (i.e. the
+ // third operand) it was fused from, as it is the only operand which
+ // still has FMF (see isCFMulFromFMSUBADD for the pattern).
+ SDValue Fmulc = DAG.getNode(X86ISD::VFCMULC, dl, CVT, MulOp0, MulOp1,
+ N2->getFlags());
+ return DAG.getBitcast(VT, Fmulc);
+ }
+ }
+
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
bool CodeSize = DAG.getMachineFunction().getFunction().hasOptSize();
bool LegalOperations = !DCI.isBeforeLegalizeOps();
- SDValue N2 = N->getOperand(2);
-
SDValue NegN2 =
TLI.getCheaperNegatedExpression(N2, DAG, LegalOperations, CodeSize);
if (!NegN2)
@@ -64221,7 +64231,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::FMADDSUB_RND:
case X86ISD::FMSUBADD_RND:
case X86ISD::FMADDSUB:
- case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, DCI);
+ case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, Subtarget, DCI);
case X86ISD::MOVMSK: return combineMOVMSK(N, DAG, DCI, Subtarget);
case X86ISD::TESTP: return combineTESTP(N, DAG, DCI, Subtarget);
case X86ISD::MGATHER:
diff --git a/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll b/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
index 741abc13584b7..c2ff3c51b5705 100644
--- a/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
+++ b/llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd.ll
@@ -4,13 +4,8 @@
define <8 x half> @test_128(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_128:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpshuflw {{.*#+}} xmm2 = xmm1[0,0,2,2,4,5,6,7]
-; CHECK-NEXT: vpshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,4,6,6]
-; CHECK-NEXT: vprold $16, %xmm0, %xmm3
-; CHECK-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[1,1,3,3,4,5,6,7]
-; CHECK-NEXT: vpshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,5,7,7]
-; CHECK-NEXT: vmulph %xmm1, %xmm3, %xmm1
-; CHECK-NEXT: vfmsubadd213ph %xmm1, %xmm2, %xmm0
+; CHECK-NEXT: vfcmulcph %xmm1, %xmm0, %xmm2
+; CHECK-NEXT: vmovaps %xmm2, %xmm0
; CHECK-NEXT: retq
%dup_even_b = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
%mul_re = fmul contract <8 x half> %a, %dup_even_b
@@ -26,13 +21,8 @@ define <8 x half> @test_128(<8 x half> %a, <8 x half> %b) {
define <16 x half> @test_256(<16 x half> %a, <16 x half> %b) {
; CHECK-LABEL: test_256:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpshuflw {{.*#+}} ymm2 = ymm1[0,0,2,2,4,5,6,7,8,8,10,10,12,13,14,15]
-; CHECK-NEXT: vpshufhw {{.*#+}} ymm2 = ymm2[0,1,2,3,4,4,6,6,8,9,10,11,12,12,14,14]
-; CHECK-NEXT: vprold $16, %ymm0, %ymm3
-; CHECK-NEXT: vpshuflw {{.*#+}} ymm1 = ymm1[1,1,3,3,4,5,6,7,9,9,11,11,12,13,14,15]
-; CHECK-NEXT: vpshufhw {{.*#+}} ymm1 = ymm1[0,1,2,3,5,5,7,7,8,9,10,11,13,13,15,15]
-; CHECK-NEXT: vmulph %ymm3, %ymm1, %ymm1
-; CHECK-NEXT: vfmsubadd213ph %ymm1, %ymm2, %ymm0
+; CHECK-NEXT: vfcmulcph %ymm1, %ymm0, %ymm2
+; CHECK-NEXT: vmovaps %ymm2, %ymm0
; CHECK-NEXT: retq
%dup_even_b = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
%mul_re = fmul contract <16 x half> %dup_even_b, %a
@@ -48,13 +38,8 @@ define <16 x half> @test_256(<16 x half> %a, <16 x half> %b) {
define <32 x half> @test_512(<32 x half> %a, <32 x half> %b) {
; CHECK-LABEL: test_512:
; CHECK: # %bb.0:
-; CHECK-NEXT: vpshuflw {{.*#+}} zmm2 = zmm1[0,0,2,2,4,5,6,7,8,8,10,10,12,13,14,15,16,16,18,18,20,21,22,23,24,24,26,26,28,29,30,31]
-; CHECK-NEXT: vpshufhw {{.*#+}} zmm2 = zmm2[0,1,2,3,4,4,6,6,8,9,10,11,12,12,14,14,16,17,18,19,20,20,22,22,24,25,26,27,28,28,30,30]
-; CHECK-NEXT: vprold $16, %zmm0, %zmm3
-; CHECK-NEXT: vpshuflw {{.*#+}} zmm1 = zmm1[1,1,3,3,4,5,6,7,9,9,11,11,12,13,14,15,17,17,19,19,20,21,22,23,25,25,27,27,28,29,30,31]
-; CHECK-NEXT: vpshufhw {{.*#+}} zmm1 = zmm1[0,1,2,3,5,5,7,7,8,9,10,11,13,13,15,15,16,17,18,19,21,21,23,23,24,25,26,27,29,29,31,31]
-; CHECK-NEXT: vmulph %zmm1, %zmm3, %zmm1
-; CHECK-NEXT: vfmsubadd213ph %zmm1, %zmm2, %zmm0
+; CHECK-NEXT: vfcmulcph %zmm1, %zmm0, %zmm2
+; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq
%dup_even_b = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14, i32 16, i32 16, i32 18, i32 18, i32 20, i32 20, i32 22, i32 22, i32 24, i32 24, i32 26, i32 26, i32 28, i32 28, i32 30, i32 30>
%mul_re = fmul contract <32 x half> %dup_even_b, %a
>From 2f42e5d06997ba00dfd5c998978e1a1c6c4611d5 Mon Sep 17 00:00:00 2001
From: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: Fri, 18 Sep 2026 12:23:43 +0530
Subject: [PATCH 3/5] format
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e67d6fd8879e6..7e2071daaa16c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58571,8 +58571,8 @@ static SDValue combineFMADDSUB(SDNode *N, SelectionDAG &DAG,
// FMSUBADD has no flags, so we use the flags from the FMUL (i.e. the
// third operand) it was fused from, as it is the only operand which
// still has FMF (see isCFMulFromFMSUBADD for the pattern).
- SDValue Fmulc = DAG.getNode(X86ISD::VFCMULC, dl, CVT, MulOp0, MulOp1,
- N2->getFlags());
+ SDValue Fmulc =
+ DAG.getNode(X86ISD::VFCMULC, dl, CVT, MulOp0, MulOp1, N2->getFlags());
return DAG.getBitcast(VT, Fmulc);
}
}
>From 043abd1b1152e453463f3597900e167bf9be948c Mon Sep 17 00:00:00 2001
From: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: Fri, 18 Sep 2026 16:59:59 +0530
Subject: [PATCH 4/5] comment
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7e2071daaa16c..cacc95a74c344 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58554,8 +58554,8 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
// Combine FMADDSUB(A, B, FNEG(C)) -> FMSUBADD(A, B, C)
// Combine FMSUBADD(A, B, FNEG(C)) -> FMADDSUB(A, B, C)
static SDValue combineFMADDSUB(SDNode *N, SelectionDAG &DAG,
- const X86Subtarget &Subtarget,
- TargetLowering::DAGCombinerInfo &DCI) {
+ TargetLowering::DAGCombinerInfo &DCI,
+ const X86Subtarget &Subtarget) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
SDValue N2 = N->getOperand(2);
@@ -64231,7 +64231,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::FMADDSUB_RND:
case X86ISD::FMSUBADD_RND:
case X86ISD::FMADDSUB:
- case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, Subtarget, DCI);
+ case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, DCI, Subtarget);
case X86ISD::MOVMSK: return combineMOVMSK(N, DAG, DCI, Subtarget);
case X86ISD::TESTP: return combineTESTP(N, DAG, DCI, Subtarget);
case X86ISD::MGATHER:
>From 81f0e875c8ddc0a1faf05fa95b161f0330a2005f Mon Sep 17 00:00:00 2001
From: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: Tue, 22 Sep 2026 11:57:08 +0530
Subject: [PATCH 5/5] fix comment
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cacc95a74c344..a012262735c0a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58550,7 +58550,7 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
}
}
-// Combine FMSUBADD(A, B, C) -> VFCMULC(A, B) for fp16 (complex)
+// Combine FMSUBADD(SHUFFLE(B),A,FMUL(SHUFFLE(A),SHUFFLE(B))) -> VFCMULC(A,B)
// Combine FMADDSUB(A, B, FNEG(C)) -> FMSUBADD(A, B, C)
// Combine FMSUBADD(A, B, FNEG(C)) -> FMADDSUB(A, B, C)
static SDValue combineFMADDSUB(SDNode *N, SelectionDAG &DAG,
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