[llvm] [DAG][X86] Bitfield insertion can combine into SHL + SHRD (PR #220182)

[Pratyay Pande via llvm-commits]

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@@ -32343,8 +32343,43 @@ static SDValue LowerFunnelShift(SDValue Op, const X86Subtarget &Subtarget,
     return DAG.getZExtOrTrunc(Res, DL, VT);
   }
 
-  if (VT == MVT::i8 || ExpandFunnel)
+  // If expanding the funnel shift is required OR the value type is unsupported
+  if (VT == MVT::i8 || ExpandFunnel) {
+    // DAG Combiner would combine an OR on a masked value and a shifted value
+    // into a shift followed by a funnel shift. The following fold reverses that
+    // operation in case `ExpandFunnel` is set, i.e., if we are not optimizing
+    // for size and if funnel-shift is slow. The fold applies if one operand is
+    // the result of an ISD::SHL or the node is MVT::i8, for which X86 does not
+    // have a funnel-shift instruction.
+    if (Op1.getOpcode() == ISD::SHL && isa<ConstantSDNode>(Amt.getNode())) {
+
+      auto *C = dyn_cast<ConstantSDNode>(Amt.getNode());
+      SDValue SHLOperandShiftAmount = Op1->getOperand(1);
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pratyaypande wrote:

Done

https://github.com/llvm/llvm-project/pull/220182