[llvm] [DAG][X86] Bitfield insertion can combine into SHL + SHRD (PR #220182)

[Pratyay Pande via llvm-commits]

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@@ -8844,6 +8844,44 @@ static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1,
   return SDValue();
 }
 
+// Fold an OR with a masked destination and a left-shifted
+// source into a shift + double-precision shift (SHRD):
+static SDValue combineOrOnSHLToFSHR(SDNode *N, SDLoc &DL, SelectionDAG &DAG) {
+  EVT VT = N->getValueType(0);
+
+  APInt Mask, ShiftAmount;
+  SDValue X, Y;
+
+  // Check for the following pattern:
+  //   (or (and X, HighBitsMask(C)), (srl Y, C))
+  // Do not combine if there are multi-use AND and OR.
+  // It does not result in more performant code.
+  if (!sd_match(N, m_Or(m_OneUse(m_And(m_Value(X), m_ConstInt(Mask))),
+                        m_OneUse(m_Shl(m_Value(Y), m_ConstInt(ShiftAmount))))))
+    return SDValue();
+
+  // Max bit-width of operands
+  uint64_t MaxMaskBitWidth = VT.getScalarSizeInBits();
+
+  // Check for Mask and ShiftAmount
+  //
+  // (shl Y, ShiftAmount) fills the top (MaxMaskBitWidth - ShiftAmount) bits,
+  // so X must keep exactly the low ShiftAmount.
+  APInt ExpectedMask =
+      APInt::getLowBitsSet(MaxMaskBitWidth, ShiftAmount.getZExtValue());
+
+  if (!((ShiftAmount.getZExtValue() > 0) &&
+        (ShiftAmount.getZExtValue() < MaxMaskBitWidth) &&
+        (Mask == ExpectedMask)))
+    return SDValue();
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pratyaypande wrote:

Done

https://github.com/llvm/llvm-project/pull/220182