[llvm] 22fc5f5 - [RISCV][MC] Reject invalid combined immediates for cv.insert in the disassembler (#225269)

[via llvm-commits]

Author: Zeyi Xu
Date: 2026-09-22T12:47:58+08:00
New Revision: 22fc5f54fa0e1a16b68126329afbebcc39960311

URL: https://github.com/llvm/llvm-project/commit/22fc5f54fa0e1a16b68126329afbebcc39960311
DIFF: https://github.com/llvm/llvm-project/commit/22fc5f54fa0e1a16b68126329afbebcc39960311.diff

LOG: [RISCV][MC] Reject invalid combined immediates for cv.insert in the disassembler (#225269)

Follow up of #224985

Added: 
    llvm/test/MC/Disassembler/RISCV/xcvbitmanip-invalid.txt

Modified: 
    llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 23fdfa2594a2f..eb7823ade07d4 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -443,6 +443,15 @@ static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeCVInsertIs2Operand(MCInst &Inst, uint32_t Imm,
+                                             int64_t Address,
+                                             const MCDisassembler *Decoder) {
+  const int64_t Is3 = Inst.getOperand(Inst.getNumOperands() - 1).getImm();
+  if (Is3 + Imm >= 32)
+    return MCDisassembler::Fail;
+  return decodeUImmOperand<5>(Inst, Imm, Address, Decoder);
+}
+
 static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
                                     uint64_t Address,
                                     const MCDisassembler *Decoder) {

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 72b2027dca1dc..9c7b0508915a6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -31,6 +31,10 @@ def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
 def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
 def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
 
+def cv_insert_is2 : RISCVUImmOp<5> {
+  let DecoderMethod = "decodeCVInsertIs2Operand";
+}
+
 def CV_LO5: SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getZExtValue() & 0x1f, SDLoc(N),
                                    N->getValueType(0));
@@ -354,7 +358,7 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
 
   let Constraints = "$rd = $rd_wb" in {
     def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
-                             (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
+                             (ins GPR:$rd, GPR:$rs1, uimm5:$is3, cv_insert_is2:$is2),
                              "cv.insert", "$rd, $rs1, $is3, $is2">;
     let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
     def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),

diff  --git a/llvm/test/MC/Disassembler/RISCV/xcvbitmanip-invalid.txt b/llvm/test/MC/Disassembler/RISCV/xcvbitmanip-invalid.txt
new file mode 100644
index 0000000000000..8b98dbf4201d9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/RISCV/xcvbitmanip-invalid.txt
@@ -0,0 +1,17 @@
+# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+xcvbitmanip < %s 2>&1 | FileCheck %s
+
+[0x5b,0x85,0x05,0xa1]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NOT: cv.insert a0, a1, 16, 16
+
+[0x5b,0x85,0xf5,0x83]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NOT: cv.insert a0, a1, 1, 31
+
+[0x5b,0x85,0x15,0xbe]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NOT: cv.insert a0, a1, 31, 1
+
+[0x5b,0x85,0xf5,0xbf]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NOT: cv.insert a0, a1, 31, 31