[clang] [llvm] [X86] Add ACE v1 (AI Compute Extensions) support (PR #208408)

[via llvm-commits]

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@@ -0,0 +1,417 @@
+//===---- X86InstrACE.td - ACE Instruction Set Extension --*- tablegen -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the ACE (AI Compute
+// Extensions) instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// ACE instructions
+
+let Predicates = [HasACEV1, In64BitMode] in {
+
+// BSRINIT - Initialize Block Scale Register
+// VEX.128.F2.0F38.W1 49 11:000:000 - BSRINIT bsr0
+// BSR is implicit destination, ModRM = 11:000:000 (mod=11, reg=000, r/m=000)
+// Note: BSR0 is implicit (via Defs), not in operand list. Asm syntax has no explicit operand.
+let SchedRW = [WriteSystem], hasSideEffects = 1, Defs = [BSR0] in {
+  def BSRINIT : I<0x49, MRM_C0, (outs), (ins),
+                  "bsrinit", []>,
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ganeshgit wrote:

Done. We didn't use ins because it is not yet a register class per se. Now addressed via printing bsr! Issues error  "too few operands for instruction" if it is not there.

https://github.com/llvm/llvm-project/pull/208408