[clang] [llvm] [RISCV] Add a command line option to disable register overlap for vector indexed load. (PR #224739)

[Craig Topper via llvm-commits]

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@@ -27003,6 +27003,20 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
 
 void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
                                                         SDNode *Node) const {
+  if (!Subtarget.allowVectorIndexLoadOverlap()) {
+    const RISCVVPseudosTable::PseudoInfo *RVV =
+        RISCVVPseudosTable::getPseudoInfo(MI.getOpcode());
+    if (RVV && (RVV->BaseInstr == RISCV::VLUXEI8_V ||
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topperc wrote:

The code for that looks a lot less efficient. We end up doing a comparison against 156 different opcodes.

https://github.com/llvm/llvm-project/pull/224739