[llvm] [IR][REVEC] Define llvm.vector.broadcast intrinsic (PR #208212)

[Gaëtan Bossu via llvm-commits]

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@@ -1965,6 +1965,22 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::VECTOR_SPLICE_RIGHT, VT, Custom);
     }
 
+    // Direct patterns exist for quad broadcasts.
+    for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64,
+                    MVT::nxv8f16, MVT::nxv4f32, MVT::nxv2f64, MVT::nxv8bf16})
+      setOperationAction(ISD::VECTOR_REPEAT, VT, Legal);
+
+    // VECTOR_REPEAT to unpacked SVE types require explicit unpacking to add
+    // spacing between elements.
+    for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv2f32, MVT::nxv2bf16,
+                    MVT::nxv4bf16})
+      setOperationAction(ISD::VECTOR_REPEAT, VT, Custom);
+
+    // VECTOR_REPEAT to nxv1 types is just a VECTOR_SPLAT
+    for (auto VT : {MVT::nxv1f16, MVT::nxv1f32, MVT::nxv1f64, MVT::nxv1bf16,
+                    MVT::nxv1i8, MVT::nxv1i16, MVT::nxv1i32, MVT::nxv1i64})
+      setOperationAction(ISD::VECTOR_REPEAT, VT, Custom);
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gbossu wrote:

I thought about this and decided against it because extractelement+splat might not be profitable on all targets if it involves moving between register banks. Looking back at it, it's a bit of a far-fetched argument and I think it makes sense to canonicalise as part of `getNode`.

https://github.com/llvm/llvm-project/pull/208212