[llvm] [TableGen] Support MachineInstr rewriting in CompressInstEmitter (PR #224212)

[Sam Elliott via llvm-commits]

lenary wrote:

I will have to take some time
to think about and review this. 

There's already a fair amount of weirdness in the compression mechanism/emitter which we've run into for risc-v, but I don't want us to end up with two similar but just slightly different mechanisms for doing this.



https://github.com/llvm/llvm-project/pull/224212