[llvm] ddc7d4b - Hexagon: Don't duplicate the PC def when converting a return to L4_return (#225059)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-09-21T15:50:39+02:00
New Revision: ddc7d4b3b43be5ef26671c19035761fb84a40388

URL: https://github.com/llvm/llvm-project/commit/ddc7d4b3b43be5ef26671c19035761fb84a40388
DIFF: https://github.com/llvm/llvm-project/commit/ddc7d4b3b43be5ef26671c19035761fb84a40388.diff

LOG: Hexagon: Don't duplicate the PC def when converting a return to L4_return (#225059)

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
    llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
    llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index efb70cf54d378..13a6fd6a9f68b 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1005,11 +1005,12 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
       return;
     }
     unsigned NewOpc = Hexagon::L4_return;
-    MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
-      .addDef(Hexagon::D15)
-      .addReg(Hexagon::R30);
-    // Transfer the function live-out registers.
-    NewI->copyImplicitOps(MF, *RetI);
+    MachineInstrBuilder NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
+                                   .addDef(Hexagon::D15)
+                                   .addReg(Hexagon::R30);
+    // Avoid duplicating the pc implicit-def.
+    for (const MachineOperand &MO : drop_begin(RetI->implicit_operands()))
+      NewI.add(MO);
     MBB.erase(RetI);
   } else {
     // L2_deallocframe instruction after it.

diff  --git a/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir b/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
index ec2a55bb5ff9d..14c219bec35b9 100644
--- a/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
+++ b/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
@@ -25,5 +25,5 @@ body: |
     $r1 = A2_tfrsi 32768
     $r2 = A2_tfrsi 1
     J2_call @f1, hexagoncsr, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $r29
-    $d15 = L4_return $r30, implicit-def $pc, implicit-def $r29, implicit $framekey, implicit-def dead $pc
+    $d15 = L4_return $r30, implicit-def $pc, implicit-def $r29, implicit $framekey
 ...

diff  --git a/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir b/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
index cdcfdae270341..3c018713913a9 100644
--- a/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
+++ b/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
@@ -43,7 +43,7 @@ body:             |
     }
     BUNDLE implicit-def dead $r0, implicit-def $d15, implicit-def $r30, implicit-def $r31, implicit-def $pc, implicit-def $r29, implicit killed $r30, implicit killed $framekey {
       $r0 = A2_tfrsi 0
-      $d15 = L4_return killed $r30, implicit-def $pc, implicit-def $r29, implicit killed $framekey, implicit-def dead $pc, implicit internal killed $r0
+      $d15 = L4_return killed $r30, implicit-def $pc, implicit-def $r29, implicit killed $framekey, implicit internal killed $r0
     }
 
 ...