[llvm] 7818c91 - PowerPC: Remove LiveVariables dependency from PPCMIPeephole (#222416)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 21 05:17:09 PDT 2026
Author: Matt Arsenault
Date: 2026-09-21T14:17:04+02:00
New Revision: 7818c91f7151a50df614fae9211eedfbfd32e938
URL: https://github.com/llvm/llvm-project/commit/7818c91f7151a50df614fae9211eedfbfd32e938
DIFF: https://github.com/llvm/llvm-project/commit/7818c91f7151a50df614fae9211eedfbfd32e938.diff
LOG: PowerPC: Remove LiveVariables dependency from PPCMIPeephole (#222416)
PPCMIPeephole only used LiveVariables to keep kill/dead flags valid
after its transforms, and made no real use of the analysis.
A later LiveVariables run recomputes those flags from scratch anyway, so
just clear possbly stale kill/dead flags on changed registers.
PPCMIPeephole was the only user of LiveVariables at this point in the
pipeline, so also drop the explicit LiveVariables run before
PPCTLSDynamicCallPass, whose comment references a > 10 year old build
bot failure.
Co-authored-by: Claude (Claude-Opus-4.8)
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/test/CodeGen/PowerPC/O0-pipeline.ll
llvm/test/CodeGen/PowerPC/O3-pipeline.ll
llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir
llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
llvm/test/CodeGen/PowerPC/mi-peephole-forwarding-undef.mir
llvm/test/CodeGen/PowerPC/mi-peephole.mir
llvm/test/CodeGen/PowerPC/peephole-combineRLWINM-liveness.mir
llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir
llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir
llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir
llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
llvm/test/CodeGen/PowerPC/sext_elimination.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index a4be03cbb3e42..bf7f3df6035d8 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -5356,8 +5356,7 @@ const unsigned MAX_BINOP_DEPTH = 1;
// than once. This is done to prevent exponential recursion.
void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
MachineRegisterInfo *MRI,
- unsigned BinOpDepth,
- LiveVariables *LV) const {
+ unsigned BinOpDepth) const {
if (!Reg.isVirtual())
return;
@@ -5383,7 +5382,7 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
for (unsigned I = 1; I < OperandEnd; I += OperandStride) {
assert(MI->getOperand(I).isReg() && "Operand must be register");
promoteInstr32To64ForElimEXTSW(MI->getOperand(I).getReg(), MRI,
- BinOpDepth + 1, LV);
+ BinOpDepth + 1);
}
break;
@@ -5399,7 +5398,7 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
// If this is a copy from another register, we recursively promote the
// source.
- promoteInstr32To64ForElimEXTSW(SrcReg, MRI, BinOpDepth, LV);
+ promoteInstr32To64ForElimEXTSW(SrcReg, MRI, BinOpDepth);
return;
}
@@ -5409,7 +5408,7 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
if (SrcReg != PPC::X3)
// If this is a copy from another register, we recursively promote the
// source.
- promoteInstr32To64ForElimEXTSW(SrcReg, MRI, BinOpDepth, LV);
+ promoteInstr32To64ForElimEXTSW(SrcReg, MRI, BinOpDepth);
return;
}
case PPC::ORI:
@@ -5420,8 +5419,7 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
case PPC::XORI8:
case PPC::ORIS8:
case PPC::XORIS8:
- promoteInstr32To64ForElimEXTSW(MI->getOperand(1).getReg(), MRI, BinOpDepth,
- LV);
+ promoteInstr32To64ForElimEXTSW(MI->getOperand(1).getReg(), MRI, BinOpDepth);
break;
case PPC::AND:
case PPC::AND8:
@@ -5429,9 +5427,9 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
break;
promoteInstr32To64ForElimEXTSW(MI->getOperand(1).getReg(), MRI,
- BinOpDepth + 1, LV);
+ BinOpDepth + 1);
promoteInstr32To64ForElimEXTSW(MI->getOperand(2).getReg(), MRI,
- BinOpDepth + 1, LV);
+ BinOpDepth + 1);
break;
}
@@ -5527,16 +5525,6 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
Iter->addOperand(MI->getOperand(i));
}
- for (unsigned i = 1; i < Iter->getNumOperands(); i++) {
- MachineOperand &Operand = Iter->getOperand(i);
- if (!Operand.isReg())
- continue;
- Register OperandReg = Operand.getReg();
- if (!OperandReg.isVirtual())
- continue;
- LV->recomputeForSingleDefVirtReg(OperandReg);
- }
-
MI->eraseFromParent();
// A defined register may be used by other instructions that are 32-bit.
@@ -5545,7 +5533,6 @@ void PPCInstrInfo::promoteInstr32To64ForElimEXTSW(const Register &Reg,
// 32-bit register
BuildMI(*MBB, ++Iter, DL, get(PPC::COPY), SrcReg)
.addReg(NewDefinedReg, RegState::Kill, PPC::sub_32);
- LV->recomputeForSingleDefVirtReg(NewDefinedReg);
}
// The isSignOrZeroExtended function is recursive. The parameter BinOpDepth
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 28687ffc5338c..542e0b0701506 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -17,7 +17,6 @@
#include "PPC.h"
#include "PPCRegisterInfo.h"
#include "llvm/ADT/SmallSet.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
@@ -743,8 +742,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
}
void promoteInstr32To64ForElimEXTSW(const Register &Reg,
MachineRegisterInfo *MRI,
- unsigned BinOpDepth,
- LiveVariables *LV) const;
+ unsigned BinOpDepth) const;
bool convertToImmediateForm(MachineInstr &MI,
SmallSet<Register, 4> &RegsToUpdate,
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 71a7994750c56..7a769acbfbc77 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -34,7 +34,6 @@
#include "PPCMachineFunctionInfo.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -112,7 +111,6 @@ struct PPCMIPeephole : public MachineFunctionPass {
const PPCInstrInfo *TII;
MachineFunction *MF;
MachineRegisterInfo *MRI;
- LiveVariables *LV;
PPCMIPeephole() : MachineFunctionPass(ID) {}
@@ -139,10 +137,10 @@ struct PPCMIPeephole : public MachineFunctionPass {
MachineInstr *MI);
// A number of transformations will eliminate the definition of a register
- // as all of its uses will be removed. However, this leaves a register
- // without a definition for LiveVariables. Such transformations should
- // use this function to provide a dummy definition of the register that
- // will simply be removed by DCE.
+ // as all of its uses will be removed. However, this can leave a register
+ // used with no reaching definition until DCE removes the dead uses. Such
+ // transformations should use this function to provide a dummy definition of
+ // the register that will simply be removed by DCE.
void addDummyDef(MachineBasicBlock &MBB, MachineInstr *At, Register Reg) {
BuildMI(MBB, At, At->getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), Reg);
}
@@ -152,13 +150,10 @@ struct PPCMIPeephole : public MachineFunctionPass {
Register Dst);
public:
-
void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<LiveVariablesWrapperPass>();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachinePostDominatorTreeWrapperPass>();
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
- AU.addPreserved<LiveVariablesWrapperPass>();
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addPreserved<MachinePostDominatorTreeWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
@@ -196,7 +191,6 @@ void PPCMIPeephole::initialize(MachineFunction &MFParm) {
MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
MPDT = &getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree();
MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- LV = &getAnalysis<LiveVariablesWrapperPass>().getLV();
EntryFreq = MBFI->getEntryFreq();
TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
RegsToUpdate.clear();
@@ -498,12 +492,11 @@ bool PPCMIPeephole::simplifyCode() {
} while (SomethingChanged && FixedPointRegToImm);
}
- // Since we are deleting this instruction, we need to run LiveVariables
- // on any of its definitions that are marked as needing an update since
- // we can't run LiveVariables on a deleted register. This only needs
- // to be done for defs since uses will have their own defining
- // instructions so we won't be running LiveVariables on a deleted reg.
- auto recomputeLVForDyingInstr = [&]() {
+ // Since we are deleting this instruction, clear the kill flags on any of its
+ // definitions that are marked as needing an update: the transforms only ever
+ // invalidate kill flags by removing uses (turning a non-last use into the
+ // last one), so a conservative clear is sufficient.
+ auto clearKillsForDyingInstr = [&]() {
if (RegsToUpdate.empty())
return;
for (MachineOperand &MO : ToErase->operands()) {
@@ -516,7 +509,9 @@ bool PPCMIPeephole::simplifyCode() {
// a def of an invalid register as the instruction is going away.
if (!MRI->getUniqueVRegDef(RegToUpdate))
MO.setReg(PPC::NoRegister);
- LV->recomputeForSingleDefVirtReg(RegToUpdate);
+ MRI->clearKillFlags(RegToUpdate);
+ for (MachineOperand &Def : MRI->def_operands(RegToUpdate))
+ Def.setIsDead(false);
}
};
@@ -528,7 +523,7 @@ bool PPCMIPeephole::simplifyCode() {
if (ToErase) {
LLVM_DEBUG(dbgs() << "Deleting instruction: ");
LLVM_DEBUG(ToErase->dump());
- recomputeLVForDyingInstr();
+ clearKillsForDyingInstr();
ToErase->eraseFromParent();
ToErase = nullptr;
}
@@ -1088,7 +1083,7 @@ bool PPCMIPeephole::simplifyCode() {
// chain used to deduce sign extension to eliminate the 'extsw' will
// need to be promoted to 64-bit pseudo instructions when the 'extsw'
// is eliminated.
- TII->promoteInstr32To64ForElimEXTSW(NarrowReg, MRI, 0, LV);
+ TII->promoteInstr32To64ForElimEXTSW(NarrowReg, MRI, 0);
LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
Register TmpReg =
@@ -1386,7 +1381,7 @@ bool PPCMIPeephole::simplifyCode() {
// If the last instruction was marked for elimination,
// remove it now.
if (ToErase) {
- recomputeLVForDyingInstr();
+ clearKillsForDyingInstr();
ToErase->eraseFromParent();
ToErase = nullptr;
}
@@ -1405,11 +1400,16 @@ bool PPCMIPeephole::simplifyCode() {
Simplified |= eliminateRedundantCompare();
// If we have made any modifications and added any registers to the set of
- // registers for which we need to update the kill flags, do so by recomputing
- // LiveVariables for those registers.
+ // registers whose liveness flags may now be stale, clear those flags. A
+ // transform may remove a use (leaving a stale kill on an earlier use) or add
+ // a use of a previously dead def (leaving a stale dead flag), so clear both
+ // kinds conservatively.
for (Register Reg : RegsToUpdate) {
- if (!MRI->reg_empty(Reg))
- LV->recomputeForSingleDefVirtReg(Reg);
+ if (MRI->reg_empty(Reg))
+ continue;
+ MRI->clearKillFlags(Reg);
+ for (MachineOperand &Def : MRI->def_operands(Reg))
+ Def.setIsDead(false);
}
return Simplified;
}
@@ -2074,7 +2074,6 @@ INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTreeWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LiveVariablesWrapperPass)
INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
"PowerPC MI Peephole Optimization", false, false)
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 96892e4b7c5df..6c9c8c9db097d 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -515,15 +515,9 @@ void PPCPassConfig::addPreRegAlloc() {
&PPCVSXFMAMutateID);
}
- // FIXME: We probably don't need to run these for -fPIE.
- if (getPPCTargetMachine().isPositionIndependent()) {
- // FIXME: LiveVariables should not be necessary here!
- // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
- // LiveVariables. This (unnecessary) dependency has been removed now,
- // however a stage-2 clang build fails without LiveVariables computed here.
- addPass(&LiveVariablesID);
+ // FIXME: We probably don't need to run this for -fPIE.
+ if (getPPCTargetMachine().isPositionIndependent())
addPass(createPPCTLSDynamicCallPass());
- }
if (EnableExtraTOCRegDeps)
addPass(createPPCTOCRegDepsPass());
diff --git a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll
index b0ba623edfb0a..efe4e1a1f6294 100644
--- a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll
+++ b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll
@@ -39,8 +39,6 @@
; CHECK-NEXT: PowerPC VSX Copy Legalization
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation
-; CHECK-NEXT: Remove unreachable machine basic blocks
-; CHECK-NEXT: Live Variable Analysis
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
index f6f3cac85a8c2..f3deff6a86ea2 100644
--- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -132,16 +132,12 @@
; CHECK-NEXT: Peephole Optimizations
; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: PowerPC Reduce CR logical Operation
-; CHECK-NEXT: Remove unreachable machine basic blocks
-; CHECK-NEXT: Live Variable Analysis
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: MachinePostDominator Tree Construction
; CHECK-NEXT: Machine Cycle Info Analysis
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: PowerPC MI Peephole Optimization
; CHECK-NEXT: Remove dead machine instructions
-; CHECK-NEXT: Remove unreachable machine basic blocks
-; CHECK-NEXT: Live Variable Analysis
; CHECK-NEXT: Slot index numbering
; CHECK-NEXT: Live Interval Analysis
; CHECK-NEXT: PowerPC TLS Dynamic Call Fixup
diff --git a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
index 2432f4245b46d..438f6398a4778 100644
--- a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
@@ -1,64 +1,92 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \
# RUN: -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s
---
name: foldNewDformStore
-# CHECK: name: foldNewDformStore
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3
+ ; CHECK-LABEL: name: foldNewDformStore
+ ; CHECK: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
+ ; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
+ ; CHECK-NEXT: STD [[LI8_]], 160, [[COPY]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
%2:g8rc = LI8 0
- ; CHECK: STD killed %2, 160, killed %0
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
BLR8 implicit $lr8, implicit $rm
...
---
name: foldNewDformStoreAlignNotMatch
-# CHECK: name: foldNewDformStoreAlignNotMatch
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3
+ ; CHECK-LABEL: name: foldNewDformStoreAlignNotMatch
+ ; CHECK: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 141
+ ; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
+ ; CHECK-NEXT: STD killed [[LI8_]], 16, [[ADDI8_]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 141
%2:g8rc = LI8 0
- ; CHECK: STD killed %2, 16, killed %1
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
BLR8 implicit $lr8, implicit $rm
...
---
name: foldNewDformStoreKilledFlag
-# CHECK: name: foldNewDformStoreKilledFlag
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3
+ ; CHECK-LABEL: name: foldNewDformStoreKilledFlag
+ ; CHECK: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
+ ; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
+ ; CHECK-NEXT: STD [[ADDI8_]], 0, [[COPY]]
+ ; CHECK-NEXT: STD [[LI8_]], 160, [[COPY]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
%2:g8rc = LI8 0
- ; CHECK: STD killed %1, 0, %0
STD %1:g8rc_and_g8rc_nox0, 0, killed %0:g8rc_and_g8rc_nox0
- ; CHECK: STD killed %2, 160, killed %0
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
BLR8 implicit $lr8, implicit $rm
...
---
name: foldNewDformPreferLIOperand
-# CHECK: name: foldNewDformPreferLIOperand
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3
+ ; CHECK-LABEL: name: foldNewDformPreferLIOperand
+ ; CHECK: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 [[COPY]], 1
+ ; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 1
+ ; CHECK-NEXT: [[SUBFIC8_:%[0-9]+]]:g8rc = SUBFIC8 [[ADDI8_]], 1, implicit-def $carry
+ ; CHECK-NEXT: [[SUBFE8_:%[0-9]+]]:g8rc = SUBFE8 [[LI8_]], [[LI8_]], implicit-def dead $carry, implicit $carry
+ ; CHECK-NEXT: [[NEG8_:%[0-9]+]]:g8rc = NEG8 killed [[SUBFE8_]]
+ ; CHECK-NEXT: $x3 = COPY [[NEG8_]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc = ADDI8 %0:g8rc_and_g8rc_nox0, 1
%2:g8rc = LI8 1
- ; CHECK: SUBFIC8 killed %1, 1, implicit-def $carry
%3:g8rc = SUBFC8 killed %1:g8rc, %2:g8rc, implicit-def $carry
%4:g8rc = SUBFE8 %2:g8rc, %2:g8rc, implicit-def dead $carry, implicit $carry
%5:g8rc = NEG8 killed %4:g8rc
@@ -72,11 +100,17 @@ tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3
+ ; CHECK-LABEL: name: killFlagSameBlock
+ ; CHECK: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], -8
+ ; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
+ ; CHECK-NEXT: STD [[LI8_]], 8, [[COPY]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 killed %0:g8rc_and_g8rc_nox0, -8
- ; CHECK: %1:g8rc_and_g8rc_nox0 = ADDI8 %0, -8
%2:g8rc = LI8 0
- ; CHECK: STD killed %2, 8, killed %0
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
BLR8 implicit $lr8, implicit $rm
...
@@ -85,15 +119,25 @@ name: killFlagDifferentBlocks
#CHECK : name : killFlagDifferentBlocks
tracksRegLiveness: true
body: |
+ ; CHECK-LABEL: name: killFlagDifferentBlocks
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], -8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
+ ; CHECK-NEXT: STD [[LI8_]], 8, [[COPY]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm
bb.0.entry:
liveins: $x3
%0:g8rc_and_g8rc_nox0 = COPY $x3
- ; CHECK: %1:g8rc_and_g8rc_nox0 = ADDI8 %0, -8
%1:g8rc_and_g8rc_nox0 = ADDI8 killed %0:g8rc_and_g8rc_nox0, -8
bb.1:
%2:g8rc = LI8 0
- ; CHECK: STD killed %2, 8, killed %0
STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
BLR8 implicit $lr8, implicit $rm
...
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
index 84b3f160c81a6..b9ca97a8bd68f 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -256,7 +256,8 @@ body: |
%3 = IMPLICIT_DEF
%2 = LI 170
%4 = RLWNM killed %1, %2, 20, 27
- ; CHECK: RLWINM killed %1, 10, 20, 27
+ ; CHECK: RLWINM %1, 10, 20, 27
+
; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
$x3 = EXTSW_32_64 %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -304,7 +305,8 @@ body: |
%0 = LI8 234
%1 = COPY $x3
%2 = RLWNM8 %1, %0, 20, 27
- ; CHECK: RLWINM8 killed %1, 10, 20, 27
+ ; CHECK: RLWINM8 %1, 10, 20, 27
+
; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
$x3 = COPY %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -484,7 +486,8 @@ body: |
%2 = COPY %1.sub_32
%5 = LI 210
%8 = SLW killed %2, killed %5
- ; CHECK: RLWINM killed %2, 18, 0, 13
+ ; CHECK: RLWINM %2, 18, 0, 13
+
; CHECK-LATE: slwi 3, 4, 18
$x3 = EXTSW_32_64 %8
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -835,7 +838,8 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 140
%4 = RLDCL %0, killed %3, 0
- ; CHECK: RLDICL killed %0, 12, 0
+ ; CHECK: RLDICL %0, 12, 0
+
; CHECK-LATE: rotldi 3, 3, 12
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -945,7 +949,8 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 300
%4 = RLDCR %0, killed %3, 0
- ; CHECK: RLDICR killed %0, 44, 0
+ ; CHECK: RLDICR %0, 44, 0
+
; CHECK-LATE: rldicr 3, 3, 44, 0
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1159,7 +1164,8 @@ body: |
%0 = COPY $x3
%2 = LI 400
%3 = SRD %0, killed %2
- ; CHECK: RLDICL killed %0, 48, 16
+ ; CHECK: RLDICL %0, 48, 16
+
; CHECK-LATE: rldicl 3, 3, 48, 16
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1265,7 +1271,8 @@ body: |
%0 = COPY $x3
%2 = LI -44
%3 = SRAD %0, killed %2, implicit-def dead $carry
- ; CHECK: SRAD killed %0, killed %2, implicit-def dead $carry
+ ; CHECK: SRAD %0, killed %2, implicit-def dead $carry
+
; CHECK-LATE: srad 3, 3, 4
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1318,7 +1325,8 @@ body: |
%0 = COPY $x3
%2 = LI 68
%3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: SRAD_rec killed %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+
; CHECK-LATE: srad. 3, 3, 5
%4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index afe8dd90db566..3462bbf3a7e9e 100644
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -1059,8 +1059,10 @@ body: |
%3 = COPY %0.sub_32
%4 = ADD4 killed %3, %2
%5 = ADD4 killed %2, killed %4
- ; CHECK: ADDI killed %3, 33
- ; CHECK: ADDI killed %4, 33
+ ; CHECK: ADDI %3, 33
+
+ ; CHECK: ADDI %4, 33
+
; CHECK-LATE: addi 3, 3, 33
; CHECK-LATE: addi 3, 3, 33
%6 = EXTSW_32_64 killed %5
@@ -1113,8 +1115,10 @@ body: |
%0 = COPY $x3
%2 = ADD8 %0, %1
%3 = ADD8 killed %1, killed %2
- ; CHECK: ADDI8 killed %0, 33
- ; CHECK: ADDI8 killed %2, 33
+ ; CHECK: ADDI8 %0, 33
+
+ ; CHECK: ADDI8 %2, 33
+
; CHECK-LATE: addi 3, 3, 33
; CHECK-LATE: addi 3, 3, 33
$x3 = COPY %3
@@ -1176,7 +1180,8 @@ body: |
%4 = COPY %0.sub_32
%5 = LI 55
%6 = ADDC %5, %4, implicit-def $carry
- ; CHECK: ADDIC killed %4, 55, implicit-def $carry
+ ; CHECK: ADDIC %4, 55, implicit-def $carry
+
; CHECK-LATE: addic 3, 3, 55
%7 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
%8 = EXTSW_32_64 %6
@@ -1235,7 +1240,8 @@ body: |
%1 = COPY $x4
%0 = LI8 777
%4 = ADDC8 %2, %0, implicit-def $carry
- ; CHECK: ADDIC8 killed %2, 777, implicit-def $carry
+ ; CHECK: ADDIC8 %2, 777, implicit-def $carry
+
; CHECK-LATE: addic 3, 5, 777
%5 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
$x3 = COPY %4
@@ -1293,7 +1299,8 @@ body: |
%0 = COPY $x3
%2 = COPY %0.sub_32
%3 = ADDC_rec %1, %2, implicit-def $cr0, implicit-def $carry
- ; CHECK: ADDIC_rec killed %2, 433, implicit-def $cr0, implicit-def dead $carry
+ ; CHECK: ADDIC_rec %2, 433, implicit-def $cr0, implicit-def $carry
+
; CHECK-LATE: addic. 3, 3, 433
%4 = COPY killed $cr0
%5 = COPY %4.sub_eq
@@ -1615,7 +1622,8 @@ body: |
%0 = LI8 89
%2 = CMPDI %0, 87
%4 = ISEL8 $zero8, %0, %2.sub_gt
- ; CHECK: ADDI8 killed %1, 0
+ ; CHECK: ADDI8 %1, 0
+
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1668,7 +1676,8 @@ body: |
%0 = LI8 87
%2 = CMPDI %0, 87
%4 = ISEL8 $zero8, %0, %2.sub_gt
- ; CHECK: COPY killed %0
+ ; CHECK: COPY %0
+
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1775,7 +1784,8 @@ body: |
%0 = LI8 65534
%2 = CMPLDI %0, 65535
%4 = ISEL8 $zero8, %0, %2.sub_gt
- ; CHECK: COPY killed %0
+ ; CHECK: COPY %0
+
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1892,7 +1902,8 @@ body: |
%3 = LI -3
%4 = CMPWI %3, 87
%6 = ISEL $zero, %3, %4.sub_gt
- ; CHECK: COPY killed %3
+ ; CHECK: COPY %3
+
%7 = ADD4 killed %6, killed %2
%8 = EXTSW_32_64 killed %7
$x3 = COPY %8
@@ -2017,7 +2028,8 @@ body: |
%3 = LI -3
%4 = CMPLWI %3, 87
%6 = ISEL $zero, %3, %4.sub_gt
- ; CHECK: ADDI killed %2, 0
+ ; CHECK: ADDI %2, 0
+
%7 = ADD4 killed %6, killed %2
%9 = IMPLICIT_DEF
%8 = INSERT_SUBREG %9, killed %7, %subreg.sub_32
@@ -2094,7 +2106,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -15
%12,%17 = LBZUX %0, killed %11 :: (load (s8) from %ir.arrayidx3, !tbaa !3)
- ; CHECK: LBZU -15, killed %0
+ ; CHECK: LBZU -15, %0
+
; CHECK-LATE: lbzu 5, -15(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2166,14 +2179,16 @@ body: |
%4 = INSERT_SUBREG %5, killed %3, %subreg.sub_32
%6 = RLDICL killed %4, 0, 32
%7 = LBZX %0, killed %6 :: (load (s8) from %ir.arrayidx, !tbaa !3)
- ; CHECK: LBZ 45, killed %6
+ ; CHECK: LBZ 45, %6
+
; CHECK-LATE: lbz 5, 45(5)
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = RLDICL killed %9, 0, 32
%12 = LBZX %0, killed %11 :: (load (s8) from %ir.arrayidx3, !tbaa !3)
- ; CHECK: LBZ 45, killed %11
+ ; CHECK: LBZ 45, %11
+
; CHECK-LATE: lbz 3, 45(4)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2251,7 +2266,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 31440
%12,%17 = LHZUX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHZU 31440, killed %0
+ ; CHECK: LHZU 31440, %0
+
; CHECK-LATE: lhzu 5, 31440(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2328,7 +2344,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 882
%12 = LHZX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHZ 882, killed %0
+ ; CHECK: LHZ 882, %0
+
; CHECK-LATE: lhz 3, 882(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2406,7 +2423,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 400
%12,%17 = LHAUX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHAU 400, killed %0
+ ; CHECK: LHAU 400, %0
+
; CHECK-LATE: lhau 5, 400(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2485,7 +2503,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 999
%12 = LHAX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
- ; CHECK: LHA 999, killed %0
+ ; CHECK: LHA 999, %0
+
; CHECK-LATE: lha 3, 999(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2566,7 +2585,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -2
%12,%18 = LWZUX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !8)
- ; CHECK: LWZU -2, killed %0
+ ; CHECK: LWZU -2, %0
+
; CHECK-LATE: lwzu {{[0-9]+}}, -2({{[0-9]+}})
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2638,14 +2658,16 @@ body: |
%4 = INSERT_SUBREG %5, killed %3, %subreg.sub_32
%6 = RLDIC %4, 2, 30
%7 = LWZX %0, killed %6 :: (load (s32) from %ir.arrayidx, !tbaa !8)
- ; CHECK: LWZ 1000, killed %6
+ ; CHECK: LWZ 1000, %6
+
; CHECK-LATE: lwz 5, 1000(5)
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = RLDIC %9, 2, 30
%12 = LWZX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !8)
- ; CHECK: LWZ 1000, killed %11
+ ; CHECK: LWZ 1000, %11
+
; CHECK-LATE: lwz 3, 1000(4)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
@@ -2714,14 +2736,16 @@ body: |
%4 = INSERT_SUBREG %5, killed %3, %subreg.sub_32
%6 = RLDIC %4, 2, 30
%7 = LWAX %0, killed %6 :: (load (s32) from %ir.arrayidx, !tbaa !8)
- ; CHECK: LWA 444, killed %6
+ ; CHECK: LWA 444, %6
+
; CHECK-LATE: lwa 5, 444(5)
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = RLDIC %9, 2, 30
%12 = LWAX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !8)
- ; CHECK: LWA 444, killed %11
+ ; CHECK: LWA 444, %11
+
; CHECK-LATE: lwa 3, 444(4)
%13 = ADD8 killed %12, killed %7
$x3 = COPY %13
@@ -2796,7 +2820,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 200
%12,%15 = LDUX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !10)
- ; CHECK: LDU 200, killed %0
+ ; CHECK: LDU 200, %0
+
; CHECK-LATE: ldu {{[0-9]+}}, 200({{[0-9]+}})
%13 = ADD8 killed %12, killed %7
$x3 = COPY %13
@@ -2869,7 +2894,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 280
%12 = LDX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !10)
- ; CHECK: LD 280, killed %0
+ ; CHECK: LD 280, %0
+
; CHECK-LATE: ld 3, 280(3)
%13 = ADD8 killed %12, killed %7
$x3 = COPY %13
@@ -2944,7 +2970,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 16
%12,%15 = LFDUX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !12)
- ; CHECK: LFDU 16, killed %0
+ ; CHECK: LFDU 16, %0
+
; CHECK-LATE: lfdu {{[0-9]+}}, 16({{[0-9]+}})
%13 = FADD killed %7, killed %12, implicit $rm
$f1 = COPY %13
@@ -3010,14 +3037,16 @@ body: |
%4 = INSERT_SUBREG %5, killed %3, %subreg.sub_32
%6 = RLDIC %4, 3, 29
%7 = LFDX %0, killed %6 :: (load (s64) from %ir.arrayidx, !tbaa !12)
- ; CHECK: LFD -20, killed %6
+ ; CHECK: LFD -20, %6
+
; CHECK-LATE: lfd {{[0-9]+}}, -20({{[0-9]+}})
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = RLDIC %9, 3, 29
%12 = LFDX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !12)
- ; CHECK: LFD -20, killed %11
+ ; CHECK: LFD -20, %11
+
; CHECK-LATE: lfd {{[0-9]+}}, -20({{[0-9]+}})
%13 = FADD killed %7, killed %12, implicit $rm
$f1 = COPY %13
@@ -3110,7 +3139,8 @@ body: |
%0 = COPY $x3
%2 = LI8 72
%3, %4 = LFSUX %0, killed %2 :: (load (s32) from %ir.arrayidx, !tbaa !14)
- ; CHECK: LFSU 72, killed %0
+ ; CHECK: LFSU 72, %0
+
; CHECK-LATE: lfsu 0, 72(3)
%5 = FCTIWUZ killed %3, implicit $rm
%6 = ADDI8 %stack.4, 0
@@ -3207,7 +3237,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -88
%12 = LFSX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !14)
- ; CHECK: LFS -88, killed %0
+ ; CHECK: LFS -88, %0
+
; CHECK-LATE: lfs 1, -88(3)
%13 = FADDS killed %7, killed %12, implicit $rm
$f1 = COPY %13
@@ -3280,7 +3311,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -120
%12 = LXSDX %0, killed %11, implicit $rm :: (load (s64) from %ir.arrayidx3, !tbaa !12)
- ; CHECK: DFLOADf64 -120, killed %0
+ ; CHECK: DFLOADf64 -120, %0, implicit $rm
+
; CHECK-LATE: lfd 1, -120(3)
%13 = XSADDDP killed %7, killed %12, implicit $rm
$f1 = COPY %13
@@ -3353,7 +3385,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -92
%12 = LXSSPX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !14)
- ; CHECK: DFLOADf32 -92, killed %0
+ ; CHECK: DFLOADf32 -92, %0
+
; CHECK-LATE: lfs 1, -92(3)
%13 = XSADDSP killed %7, killed %12
$f1 = COPY %13
@@ -3426,7 +3459,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -16
%12 = LXVX %0, killed %11 :: (load (s128) from %ir.arrayidx3, !tbaa !3)
- ; CHECK: LXV -16, killed %0
+ ; CHECK: LXV -16, %0
+
; CHECK-LATE: lxv 35, -16(3)
%13 = VADDUWM killed %12, killed %7
$v2 = COPY %13
@@ -3478,7 +3512,8 @@ body: |
%0 = LI 99
%3 = COPY %1.sub_32
%2 = OR %0, %3
- ; CHECK: ORI killed %3, 99
+ ; CHECK: ORI %3, 99
+
; CHECK-LATE: ori 3, 4, 99
$x3 = EXTSW_32_64 %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3527,7 +3562,8 @@ body: |
%1 = COPY $x4
%0 = LI8 777
%2 = OR8 %1, %0
- ; CHECK: ORI8 killed %1, 777
+ ; CHECK: ORI8 %1, 777
+
; CHECK-LATE: ori 3, 4, 777
$x3 = COPY %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3672,7 +3708,8 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 14
%4 = RLDCL %0, killed %3, 0
- ; CHECK: RLDICL killed %0, 14, 0
+ ; CHECK: RLDICL %0, 14, 0
+
; CHECK-LATE: rotldi 3, 3, 14
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3782,7 +3819,8 @@ body: |
%2 = COPY %1.sub_32
%3 = LI 0
%4 = RLDCR %0, killed %3, 0
- ; CHECK: RLDICR killed %0, 0, 0
+ ; CHECK: RLDICR %0, 0, 0
+
; CHECK-LATE: rldicr 3, 3, 0, 0
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -3982,7 +4020,8 @@ body: |
%1 = COPY $x4
%0 = LI8 -1
%2 = RLDICL_rec %0, 53, 48, implicit-def $cr0
- ; CHECK: ANDI8_rec killed %0, 65535
+ ; CHECK: ANDI8_rec %0, 65535, implicit-def $cr0
+
; CHECK-LATE: li 3, -1
; CHECK-LATE: andi. 3, 3, 65535
%3 = COPY killed $cr0
@@ -4037,7 +4076,8 @@ body: |
%0 = LI8 200
%2 = RLDICL_rec %0, 61, 3, implicit-def $cr0
; CHECK: LI8 25
- ; CHECK: ANDI8_rec killed %0, 25
+ ; CHECK: ANDI8_rec %0, 25, implicit-def $cr0
+
; CHECK-LATE-NOT: andi.
%3 = COPY killed $cr0
%4 = ISEL8 %1, %2, %3.sub_eq
@@ -4090,7 +4130,8 @@ body: |
%1 = COPY $x4
%0 = LI8 2
%2 = RLDICL_rec %0, 32, 32, implicit-def $cr0
- ; CHECK: ANDI8_rec killed %0, 0
+ ; CHECK: ANDI8_rec %0, 0, implicit-def $cr0
+
; CHECK-LATE: li 3, 2
; CHECK-LATE: andi. 3, 3, 0
%3 = COPY killed $cr0
@@ -4480,7 +4521,8 @@ body: |
%0 = COPY $x3
%2 = LI8 -18
%3 = RLWINM8_rec %2, 4, 20, 27, implicit-def $cr0
- ; CHECK: ANDI8_rec killed %2, 3808
+ ; CHECK: ANDI8_rec %2, 3808, implicit-def $cr0
+
; CHECK-LATE: li 3, -18
; CHECK-LATE: andi. 3, 3, 3808
%7 = COPY killed $cr0
@@ -4535,7 +4577,8 @@ body: |
%0 = COPY $x3
%2 = LI 13
%3 = SLD %0, killed %2
- ; CHECK: RLDICR killed %0, 13, 50
+ ; CHECK: RLDICR %0, 13, 50
+
; CHECK-LATE: sldi 3, 3, 13
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -4641,7 +4684,8 @@ body: |
%0 = COPY $x3
%2 = LI 4
%3 = SRD %0, killed %2
- ; CHECK: RLDICL killed %0, 60, 4
+ ; CHECK: RLDICL %0, 60, 4
+
; CHECK-LATE: rldicl 3, 3, 60, 4
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -4753,7 +4797,8 @@ body: |
%2 = COPY %1.sub_32
%5 = LI 21
%8 = SLW killed %2, killed %5
- ; CHECK: RLWINM killed %2, 21, 0, 10
+ ; CHECK: RLWINM %2, 21, 0, 10
+
; CHECK-LATE: slwi 3, 4, 21
$x3 = EXTSW_32_64 %8
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -4873,7 +4918,8 @@ body: |
%2 = LI 8
%5 = COPY %0.sub_32
%8 = SRW killed %5, killed %2
- ; CHECK: RLWINM killed %5, 24, 8, 31
+ ; CHECK: RLWINM %5, 24, 8, 31
+
; CHECK-LATE: srwi 3, 3, 8
$x3 = EXTSW_32_64 %8
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -4991,7 +5037,8 @@ body: |
%3 = COPY %0.sub_32
%4 = SRAW killed %3, killed %2, implicit-def dead $carry
; CHECK: %6:g8rc = IMPLICIT_DEF
- ; CHECK-NEXT: %7:g8rc = INSERT_SUBREG %6, killed %3, %subreg.sub_32
+ ; CHECK-NEXT: %7:g8rc = INSERT_SUBREG %6, %3, %subreg.sub_32
+
; CHECK-NEXT: %8:g8rc = SRAWI8 killed %7, 15, implicit-def $carry, implicit-def dead $carry
; CHECK-NEXT: %4:gprc = COPY killed %8.sub_32
; CHECK-LATE: srawi 3, 3, 15
@@ -5104,7 +5151,8 @@ body: |
%0 = COPY $x3
%2 = LI 44
%3 = SRAD %0, killed %2, implicit-def dead $carry
- ; CHECK: SRADI killed %0, 44, implicit-def dead $carry
+ ; CHECK: SRADI %0, 44, implicit-def dead $carry
+
; CHECK-LATE: sradi 3, 3, 44
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -5157,7 +5205,8 @@ body: |
%0 = COPY $x3
%2 = LI 61
%3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
- ; CHECK: SRADI_rec killed %0, 61, implicit-def dead $carry, implicit-def $cr0
+ ; CHECK: SRADI_rec %0, 61, implicit-def dead $carry, implicit-def $cr0
+
; CHECK-LATE: sradi. 3, 3, 61
%4 = COPY killed $cr0
%5 = ISEL8 %1, %3, %4.sub_eq
@@ -5235,7 +5284,8 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, %subreg.sub_32
%12 = LI8 777
%14 = STBUX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
- ; CHECK: STBU killed %3, 777, killed %0
+ ; CHECK: STBU %3, 777, %0
+
; CHECK-LATE: {{[0-9]+}}, 777({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5301,14 +5351,16 @@ body: |
%6 = INSERT_SUBREG %7, killed %5, %subreg.sub_32
%8 = RLDICL killed %6, 0, 32
STBX %3, %0, killed %8 :: (store (s8) into %ir.arrayidx, !tbaa !3)
- ; CHECK: STB %3, 975, killed %8
+ ; CHECK: STB %3, 975, %8
+
; CHECK-LATE: stb 4, 975(6)
%9 = ADDI %4, 2
%11 = IMPLICIT_DEF
%10 = INSERT_SUBREG %11, killed %9, %subreg.sub_32
%12 = RLDICL killed %10, 0, 32
STBX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
- ; CHECK: STB killed %3, 975, killed %12
+ ; CHECK: STB %3, 975, %12
+
; CHECK-LATE: stb 4, 975(5)
BLR8 implicit $lr8, implicit $rm
@@ -5383,7 +5435,8 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, %subreg.sub_32
%12 = LI8 -761
%14 = STHUX %3, %0, killed %12 :: (store (s16) into %ir.arrayidx3, !tbaa !6)
- ; CHECK: STHU killed %3, -761, killed %0
+ ; CHECK: STHU %3, -761, %0
+
; CHECK-LATE: sthu {{[0-9]+}}, -761({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5456,7 +5509,8 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, %subreg.sub_32
%12 = LI8 -900
STHX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
- ; CHECK: STH killed %3, -900, killed %0
+ ; CHECK: STH %3, -900, %0
+
; CHECK-LATE: sth {{[0-9]+}}, -900({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5531,7 +5585,8 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, %subreg.sub_32
%12 = LI8 0
%14 = STWUX %3, %0, killed %12 :: (store (s32) into %ir.arrayidx3, !tbaa !8)
- ; CHECK: STWU killed %3, 0, killed %0
+ ; CHECK: STWU %3, 0, %0
+
; CHECK-LATE: stwu {{[0-9]+}}, 0({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5604,7 +5659,8 @@ body: |
%10 = INSERT_SUBREG %11, killed %9, %subreg.sub_32
%12 = LI8 99
STWX %3, %0, killed %12 :: (store (s32) into %ir.arrayidx3, !tbaa !8)
- ; CHECK: STW killed %3, 99, killed %0
+ ; CHECK: STW %3, 99, %0
+
; CHECK-LATE: stw 4, 99(3)
BLR8 implicit $lr8, implicit $rm
@@ -5677,7 +5733,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -8
%13 = STDUX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !10)
- ; CHECK: STDU killed %1, -8, killed %0
+ ; CHECK: STDU %1, -8, %0
+
; CHECK-LATE: stdu {{[0-9]+}}, -8({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5741,14 +5798,16 @@ body: |
%5 = INSERT_SUBREG %6, killed %4, %subreg.sub_32
%7 = LI8 900
STDX %1, %0, killed %7 :: (store (s64) into %ir.arrayidx, !tbaa !10)
- ; CHECK: STD %1, 1000, killed %7
+ ; CHECK: STD %1, 1000, %7
+
; CHECK-LATE: {{[0-9]+}}, 1000({{[0-9]+}})
%8 = ADDI %3, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -900
STDX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !10)
- ; CHECK: STD killed %1, 1000, killed %11
+ ; CHECK: STD %1, 1000, %11
+
; CHECK-LATE: {{[0-9]+}}, 1000({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5819,7 +5878,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -401
STFSX %1, %0, killed %11 :: (store (s32) into %ir.arrayidx3, !tbaa !14)
- ; CHECK: STFS killed %1, -401, killed %0
+ ; CHECK: STFS %1, -401, %0
+
; CHECK-LATE: stfs 1, -401(3)
BLR8 implicit $lr8, implicit $rm
@@ -5892,7 +5952,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 987
%13 = STFSUX %1, %0, killed %11 :: (store (s32) into %ir.arrayidx3, !tbaa !14)
- ; CHECK: STFSU killed %1, 987, killed %0
+ ; CHECK: STFSU %1, 987, %0
+
; CHECK-LATE: stfsu {{[0-9]+}}, 987({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -5963,7 +6024,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 -873
STFDX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !12)
- ; CHECK: STFD killed %1, -873, killed %0
+ ; CHECK: STFD %1, -873, %0
+
; CHECK-LATE: stfd 1, -873(3)
BLR8 implicit $lr8, implicit $rm
@@ -6036,7 +6098,8 @@ body: |
%9 = INSERT_SUBREG %10, killed %8, %subreg.sub_32
%11 = LI8 6477
%13 = STFDUX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !12)
- ; CHECK: STFDU killed %1, 6477, killed %0
+ ; CHECK: STFDU %1, 6477, %0
+
; CHECK-LATE: stfdu {{[0-9]+}}, 6477({{[0-9]+}})
BLR8 implicit $lr8, implicit $rm
@@ -6088,7 +6151,8 @@ body: |
%0 = COPY $x3
%3 = LI8 444
STXSSPX %1, %0, killed %3 :: (store (s32) into %ir.arrayidx, !tbaa !14)
- ; CHECK: DFSTOREf32 killed %1, 444, killed %0
+ ; CHECK: DFSTOREf32 %1, 444, %0
+
; CHECK-LATE: stfs 1, 444(3)
BLR8 implicit $lr8, implicit $rm
@@ -6140,7 +6204,8 @@ body: |
%0 = COPY $x3
%3 = LI8 4
STXSDX %1, %0, killed %3, implicit $rm :: (store (s64) into %ir.arrayidx, !tbaa !12)
- ; CHECK: DFSTOREf64 killed %1, 4, killed %0
+ ; CHECK: DFSTOREf64 %1, 4, %0, implicit $rm
+
; CHECK-LATE: stfd 1, 4(3)
BLR8 implicit $lr8, implicit $rm
@@ -6192,7 +6257,8 @@ body: |
%0 = LI8 16
%3 = RLDICR %2, 4, 59
STXVX %1, %0, killed %3 :: (store (s128) into %ir.arrayidx, !tbaa !3)
- ; CHECK: STXV killed %1, 16, killed %3
+ ; CHECK: STXV %1, 16, %3
+
; CHECK-LATE: stxv 34, 16(4)
BLR8 implicit $lr8, implicit $rm
@@ -6253,7 +6319,8 @@ body: |
%8 = COPY %1.sub_32
%0 = LI 55
%4 = SUBFC %7, %0, implicit-def $carry
- ; CHECK: SUBFIC killed %7, 55
+ ; CHECK: SUBFIC %7, 55, implicit-def $carry
+
; CHECK-LATE: subfic 3, 5, 55
%5 = SUBFE %6, %8, implicit-def dead $carry, implicit $carry
$x3 = EXTSW_32_64 %4
@@ -6311,7 +6378,8 @@ body: |
%1 = COPY $x4
%0 = LI8 7635
%4 = SUBFC8 %2, %0, implicit-def $carry
- ; CHECK: SUBFIC8 killed %2, 7635
+ ; CHECK: SUBFIC8 %2, 7635, implicit-def $carry
+
; CHECK-LATE: subfic 3, 5, 7635
%5 = SUBFE8 %3, %1, implicit-def dead $carry, implicit $carry
$x3 = COPY %4
@@ -6364,7 +6432,8 @@ body: |
%0 = COPY $x3
%3 = COPY %0.sub_32
%2 = XOR %1, %3
- ; CHECK: XORI killed %3, 10101
+ ; CHECK: XORI %3, 10101
+
; CHECK-LATE: 3, 3, 10101
$x3 = EXTSW_32_64 %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -6413,7 +6482,8 @@ body: |
%1 = COPY $x4
%0 = LI8 5535
%2 = XOR8 %1, %0
- ; CHECK: XORI8 killed %1, 5535
+ ; CHECK: XORI8 %1, 5535
+
; CHECK-LATE: xori 3, 4, 5535
$x3 = COPY %2
BLR8 implicit $lr8, implicit $rm, implicit $x3
diff --git a/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir b/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
index 66a266e89a9f7..ba734f9325a7b 100644
--- a/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
+++ b/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
@@ -28,11 +28,11 @@ body: |
liveins: $r3
%0:gprc = COPY $r3
%1:gprc_and_gprc_nor0 = LI 0
- ; CHECK-NOT: COPY %1
%2:gprc = COPY %1:gprc_and_gprc_nor0
+ ; CHECK: %2:gprc = COPY %1
; CHECK: %3:gprc = LI 1
%3:gprc = ORI killed %2:gprc, 1
- ; CHECK: STW killed %3, killed %0, 100
+ ; CHECK: STW %3, %0, 100
STW killed %3:gprc, %0:gprc, 100
BLR8 implicit $lr8, implicit $rm
...
diff --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
index 759bccd24cc61..8288a21ef4ced 100644
--- a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
+++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
@@ -13,7 +13,8 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 5, 31
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 5, 31
%3:gprc = RLWINM %2:gprc, 19, 0, 12
- ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
+ ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -28,7 +29,8 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 0, 31
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 0, 31
%3:gprc = RLWINM %2:gprc, 19, 0, 12
- ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
+ ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -43,7 +45,8 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 10, 9
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 10, 9
%3:gprc = RLWINM %2:gprc, 19, 10, 1
- ; CHECK: %3:gprc = RLWINM killed %1, 14, 10, 1
+ ; CHECK: %3:gprc = RLWINM %1, 14, 10, 1
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -58,7 +61,8 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 30, 10
; CHECK-NOT: %2:gprc = RLWINM %1, 27, 30, 10
%3:gprc = RLWINM %2:gprc, 19, 0, 12
- ; CHECK: %3:gprc = RLWINM killed %1, 14, 11, 12
+ ; CHECK: %3:gprc = RLWINM %1, 14, 11, 12
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -71,9 +75,11 @@ body: |
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
%2:gprc = RLWINM %1:gprc, 10, 5, 31
- ; CHECK: %2:gprc = RLWINM killed %1, 10, 5, 31
+ ; CHECK: %2:gprc = RLWINM %1, 10, 5, 31
+
%3:gprc = RLWINM %2:gprc, 10, 30, 5
- ; CHECK: %3:gprc = RLWINM killed %2, 10, 30, 5
+ ; CHECK: %3:gprc = RLWINM %2, 10, 30, 5
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -103,9 +109,11 @@ body: |
%2:gprc = RLWINM killed %1:gprc, 27, 5, 31
; CHECK: %2:gprc = RLWINM %1, 27, 5, 31
%3:gprc = RLWINM %2:gprc, 19, 0, 12
- ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
+ ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+
STW %3:gprc, %2:gprc, 100
- ; CHECK: STW killed %3, killed %2, 100
+ ; CHECK: STW %3, %2, 100
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -135,7 +143,8 @@ body: |
%2:gprc = RLWINM %1:gprc, 27, 5, 10
; CHECK-NOT: RLWINM %1,
%3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
- ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
+ ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -148,9 +157,11 @@ body: |
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
%2:gprc = RLWINM_rec killed %1:gprc, 27, 5, 10, implicit-def $cr0
- ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def dead $cr0
+ ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def $cr0
+
%3:gprc = RLWINM_rec killed %2:gprc, 8, 5, 10, implicit-def $cr0
- ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
+ ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -163,9 +174,11 @@ body: |
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
%2:gprc = RLWINM %1:gprc, 20, 5, 31
- ; CHECK: %2:gprc = RLWINM killed %1, 20, 5, 31
+ ; CHECK: %2:gprc = RLWINM %1, 20, 5, 31
+
%3:gprc = RLWINM %2:gprc, 19, 10, 20
- ; CHECK: %3:gprc = RLWINM killed %2, 19, 10, 20
+ ; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
+
BLR8 implicit $lr8, implicit $rm
...
---
@@ -190,10 +203,10 @@ body: |
liveins: $x3
; CHECK-LABEL: name: testFoldRLWINMAndANDI
; CHECK: liveins: $x3
- ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
- ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 4, 28, 31
- ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec killed [[RLWINM]], 4, implicit-def dead $cr0
+ ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
+ ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 4, 28, 31
+ ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec [[RLWINM]], 4, implicit-def $cr0
; CHECK: BLR8 implicit $lr8, implicit $rm
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
diff --git a/llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir b/llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir
index 543b844fa33e6..e9ac13bd69c7a 100644
--- a/llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir
+++ b/llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir
@@ -11,11 +11,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICL_ANDI
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 32
- ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 1, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 32
+ ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec [[COPY]], 1, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDI8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICL %1:g8rc, 0, 32
%3:g8rc = ANDI8_rec killed %2:g8rc, 1, implicit-def dead $cr0
@@ -31,11 +31,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICL_ANDI2
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 10, 60
- ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 0, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 10, 60
+ ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec [[COPY]], 0, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDI8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICL %1:g8rc, 10, 60
%3:g8rc = ANDI8_rec killed %2:g8rc, 32, implicit-def dead $cr0
@@ -51,11 +51,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICR_ANDI
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 0, 60
- ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 16, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 0, 60
+ ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec [[COPY]], 16, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDI8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICR %1:g8rc, 0, 60
%3:g8rc = ANDI8_rec killed %2:g8rc, 16, implicit-def dead $cr0
@@ -71,11 +71,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICR_ANDI2
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 10, 60
- ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 0, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 10, 60
+ ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec [[COPY]], 0, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDI8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICR %1:g8rc, 10, 60
%3:g8rc = ANDI8_rec killed %2:g8rc, 1, implicit-def dead $cr0
@@ -91,11 +91,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICL_ANDIS
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 32
- ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 1, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 0, 32
+ ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec [[COPY]], 1, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDIS8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICL %1:g8rc, 0, 32
%3:g8rc = ANDIS8_rec killed %2:g8rc, 1, implicit-def dead $cr0
@@ -111,11 +111,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICL_ANDIS2
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 10, 60
- ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 0, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICL:%[0-9]+]]:g8rc = RLDICL [[COPY]], 10, 60
+ ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec [[COPY]], 0, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDIS8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICL %1:g8rc, 10, 60
%3:g8rc = ANDIS8_rec killed %2:g8rc, 16, implicit-def dead $cr0
@@ -131,11 +131,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICR_ANDIS
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 0, 60
- ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 16, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 0, 60
+ ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec [[COPY]], 16, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDIS8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICR %1:g8rc, 0, 60
%3:g8rc = ANDIS8_rec killed %2:g8rc, 16, implicit-def dead $cr0
@@ -151,11 +151,11 @@ body: |
; CHECK-LABEL: name: fold_RLDICR_ANDIS2
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; CHECK-NEXT: dead [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 10, 32
- ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 0, implicit-def dead $cr0
- ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[COPY]], 10, 32
+ ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec [[COPY]], 0, implicit-def dead $cr0
+ ; CHECK-NEXT: $x3 = COPY [[ANDIS8_rec]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x3
%2:g8rc = RLDICR %1:g8rc, 10, 32
%3:g8rc = ANDIS8_rec killed %2:g8rc, 1, implicit-def dead $cr0
diff --git a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
index 70b13298f89e4..3f805141b60a2 100644
--- a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
+++ b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
@@ -50,4 +50,5 @@ body: |
#
# CHECK-PASS-NOT: %2:g8rc = RLDICL killed %1, 0, 32
# CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
-# CHECK-PASS: %3:g8rc = RLDIC killed %1, 2, 30
+# CHECK-PASS: %3:g8rc = RLDIC %1, 2, 30
+
diff --git a/llvm/test/CodeGen/PowerPC/mi-peephole-forwarding-undef.mir b/llvm/test/CodeGen/PowerPC/mi-peephole-forwarding-undef.mir
index 8009bc6255097..6365acc18f24c 100644
--- a/llvm/test/CodeGen/PowerPC/mi-peephole-forwarding-undef.mir
+++ b/llvm/test/CodeGen/PowerPC/mi-peephole-forwarding-undef.mir
@@ -12,11 +12,11 @@ body: |
; CHECK-LABEL: name: forwarding_undef
; CHECK: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 undef %2:g8rc_and_g8rc_nox0, 4
- ; CHECK-NEXT: [[ADD8_:%[0-9]+]]:g8rc = ADD8 killed [[COPY]], killed [[ADDI8_]]
- ; CHECK-NEXT: $x3 = COPY killed [[ADD8_]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY]], [[ADDI8_]]
+ ; CHECK-NEXT: $x3 = COPY [[ADD8_]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%0:g8rc = COPY $x3
%1:g8rc = ADDI8 undef %2:g8rc_and_g8rc_nox0, 4
%3:g8rc = ADD8 %0, %1
diff --git a/llvm/test/CodeGen/PowerPC/mi-peephole.mir b/llvm/test/CodeGen/PowerPC/mi-peephole.mir
index a2cc364e28ab7..34f0e1a94f050 100644
--- a/llvm/test/CodeGen/PowerPC/mi-peephole.mir
+++ b/llvm/test/CodeGen/PowerPC/mi-peephole.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=powerpc64le--linux-gnu -run-pass ppc-mi-peepholes %s -o - \
# RUN: -verify-machineinstrs | FileCheck %s
@@ -19,6 +20,14 @@ body: |
bb.0.entry:
liveins: $x3, $x4
+ ; CHECK-LABEL: name: testRLDIC
+ ; CHECK: liveins: $x3, $x4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x4
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY $x3
+ ; CHECK-NEXT: [[RLDIC:%[0-9]+]]:g8rc = RLDIC [[COPY]], 2, 30
+ ; CHECK-NEXT: $x3 = COPY [[RLDIC]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
%1:g8rc = COPY $x4
%0:g8rc = COPY $x3
%2:g8rc = RLDICL killed %1, 0, 32
@@ -26,11 +35,4 @@ body: |
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
- ; CHECK-LABEL: testRLDIC
- ; CHECK: bb.0.entry:
- ; CHECK: %1:g8rc = COPY killed $x4
- ; CHECK: %0:g8rc = COPY killed $x3
- ; CHECK: %3:g8rc = RLDIC killed %1, 2, 30
- ; CHECK: $x3 = COPY killed %3
- ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
...
diff --git a/llvm/test/CodeGen/PowerPC/peephole-combineRLWINM-liveness.mir b/llvm/test/CodeGen/PowerPC/peephole-combineRLWINM-liveness.mir
index a5714f20f77f8..ff4bc3f7faba9 100644
--- a/llvm/test/CodeGen/PowerPC/peephole-combineRLWINM-liveness.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-combineRLWINM-liveness.mir
@@ -22,6 +22,6 @@ body: |
# CHECK-LABEL: testFoldRLWINM
# CHECK: bb.0.entry:
-# CHECK: dead %0:gprc = COPY killed $r3
+# CHECK: %0:gprc = COPY $r3
# CHECK: bb.2:
-# CHECK: dead %2:gprc = LI 0
+# CHECK: %2:gprc = LI 0
diff --git a/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir
index 638b533a32a0d..a4f61280d1ae7 100644
--- a/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir
@@ -24,53 +24,53 @@ body: |
; ALL-LABEL: name: foldDForm
; ALL: liveins: $x3
; ALL-NEXT: {{ $}}
- ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
- ; ALL-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; ALL-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
; ALL-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
; ALL-NEXT: STD [[LI8_]], 160, [[COPY]]
- ; ALL-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160
+ ; ALL-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160
; ALL-NEXT: STD [[LI8_]], 176, [[COPY]]
- ; ALL-NEXT: dead [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 176
- ; ALL-NEXT: STD killed [[LI8_]], 192, killed [[COPY]]
+ ; ALL-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 176
+ ; ALL-NEXT: STD [[LI8_]], 192, [[COPY]]
; ALL-NEXT: BLR8 implicit $lr8, implicit $rm
;
; ONE-FIRSTSTORE-LABEL: name: foldDForm
; ONE-FIRSTSTORE: liveins: $x3
; ONE-FIRSTSTORE-NEXT: {{ $}}
- ; ONE-FIRSTSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
- ; ONE-FIRSTSTORE-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
+ ; ONE-FIRSTSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; ONE-FIRSTSTORE-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
; ONE-FIRSTSTORE-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 160, [[COPY]]
; ONE-FIRSTSTORE-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160
- ; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 16, killed [[ADDI8_1]]
- ; ONE-FIRSTSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176
- ; ONE-FIRSTSTORE-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]]
+ ; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 16, [[ADDI8_1]]
+ ; ONE-FIRSTSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 176
+ ; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 16, [[ADDI8_2]]
; ONE-FIRSTSTORE-NEXT: BLR8 implicit $lr8, implicit $rm
;
; ONE-SECONDSTORE-LABEL: name: foldDForm
; ONE-SECONDSTORE: liveins: $x3
; ONE-SECONDSTORE-NEXT: {{ $}}
- ; ONE-SECONDSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
+ ; ONE-SECONDSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
; ONE-SECONDSTORE-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
; ONE-SECONDSTORE-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
- ; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 16, killed [[ADDI8_]]
- ; ONE-SECONDSTORE-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160
+ ; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 16, [[ADDI8_]]
+ ; ONE-SECONDSTORE-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160
; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 176, [[COPY]]
- ; ONE-SECONDSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176
- ; ONE-SECONDSTORE-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]]
+ ; ONE-SECONDSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 176
+ ; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 16, [[ADDI8_2]]
; ONE-SECONDSTORE-NEXT: BLR8 implicit $lr8, implicit $rm
;
; TWO-LABEL: name: foldDForm
; TWO: liveins: $x3
; TWO-NEXT: {{ $}}
- ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
- ; TWO-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
+ ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; TWO-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144
; TWO-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0
; TWO-NEXT: STD [[LI8_]], 160, [[COPY]]
- ; TWO-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160
+ ; TWO-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160
; TWO-NEXT: STD [[LI8_]], 176, [[COPY]]
- ; TWO-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176
- ; TWO-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]]
+ ; TWO-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 176
+ ; TWO-NEXT: STD [[LI8_]], 16, [[ADDI8_2]]
; TWO-NEXT: BLR8 implicit $lr8, implicit $rm
%0:g8rc_and_g8rc_nox0 = COPY $x3
%1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
diff --git a/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir b/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir
index 09f7ededa20c6..876987471b8f4 100644
--- a/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir
@@ -28,44 +28,44 @@ body: |
; ALL-LABEL: name: testFoldRLWINM
; ALL: liveins: $x3
; ALL-NEXT: {{ $}}
- ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; ALL-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
- ; ALL-NEXT: dead [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12
- ; ALL-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 11
- ; ALL-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 10
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
+ ; ALL-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12
+ ; ALL-NEXT: [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 11
+ ; ALL-NEXT: [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 10
; ALL-NEXT: BLR8 implicit $lr8, implicit $rm
;
; ONE-FIRST-RLWINM-LABEL: name: testFoldRLWINM
; ONE-FIRST-RLWINM: liveins: $x3
; ONE-FIRST-RLWINM-NEXT: {{ $}}
- ; ONE-FIRST-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; ONE-FIRST-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+ ; ONE-FIRST-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; ONE-FIRST-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
; ONE-FIRST-RLWINM-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31
- ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 12
- ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 11
- ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10
+ ; ONE-FIRST-RLWINM-NEXT: [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12
+ ; ONE-FIRST-RLWINM-NEXT: [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 11
+ ; ONE-FIRST-RLWINM-NEXT: [[RLWINM3:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 10
; ONE-FIRST-RLWINM-NEXT: BLR8 implicit $lr8, implicit $rm
;
; ONE-SECOND-RLWINM-LABEL: name: testFoldRLWINM
; ONE-SECOND-RLWINM: liveins: $x3
; ONE-SECOND-RLWINM-NEXT: {{ $}}
- ; ONE-SECOND-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; ONE-SECOND-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+ ; ONE-SECOND-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; ONE-SECOND-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
; ONE-SECOND-RLWINM-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31
- ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 12
- ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 11
- ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10
+ ; ONE-SECOND-RLWINM-NEXT: [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 12
+ ; ONE-SECOND-RLWINM-NEXT: [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 11
+ ; ONE-SECOND-RLWINM-NEXT: [[RLWINM3:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 10
; ONE-SECOND-RLWINM-NEXT: BLR8 implicit $lr8, implicit $rm
;
; TWO-LABEL: name: testFoldRLWINM
; TWO: liveins: $x3
; TWO-NEXT: {{ $}}
- ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
- ; TWO-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+ ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+ ; TWO-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
; TWO-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31
- ; TWO-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12
- ; TWO-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 11
- ; TWO-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10
+ ; TWO-NEXT: [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12
+ ; TWO-NEXT: [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 11
+ ; TWO-NEXT: [[RLWINM3:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 10
; TWO-NEXT: BLR8 implicit $lr8, implicit $rm
%0:g8rc = COPY $x3
%1:gprc = COPY %0.sub_32:g8rc
diff --git a/llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir b/llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir
index 16df0caa9e899..2f357b4704496 100644
--- a/llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux \
# RUN: -run-pass=ppc-mi-peepholes %s -o - | FileCheck %s
@@ -20,18 +21,20 @@ body: |
bb.0:
liveins: $f1
+ ; CHECK-LABEL: name: test_xxpermdi_splat_multiple_uses
+ ; CHECK: liveins: $f1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[XXLXORz:%[0-9]+]]:vrrc = XXLXORz
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:f8rc = COPY $f1
+ ; CHECK-NEXT: [[XXPERMDIs:%[0-9]+]]:vrrc = XXPERMDIs [[COPY]], 0
+ ; CHECK-NEXT: [[XXPERMDI:%[0-9]+]]:vrrc = XXPERMDI [[XXLXORz]], [[XXPERMDIs]], 3
+ ; CHECK-NEXT: [[XXPERMDI1:%[0-9]+]]:vrrc = XXPERMDI [[XXPERMDIs]], [[XXPERMDIs]], 3
%28:vrrc = XXLXORz
%31:f8rc = COPY $f1
%0:vrrc = XXPERMDIs %31, 0
%34:vrrc = XXPERMDI %28, %0, 3
%35:vrrc = XXPERMDI %0, %0, 3
- ; CHECK-LABEL: name: test_xxpermdi_splat_multiple_uses
- ; CHECK: %1:vrrc = XXLXORz
- ; CHECK-NEXT: %2:f8rc = COPY killed $f1
- ; CHECK-NEXT: %0:vrrc = XXPERMDIs killed %2, 0
- ; CHECK-NEXT: %3:vrrc = XXPERMDI killed %1, %0, 3
- ; CHECK-NEXT: %4:vrrc = XXPERMDI killed %0, %0, 3
...
---
name: test_swap_isel_livevars
@@ -53,6 +56,19 @@ registers:
- { id: 31, class: vsrc }
body: |
bb.0:
+ ; CHECK-LABEL: name: test_swap_isel_livevars
+ ; CHECK: [[LI:%[0-9]+]]:gprc = LI 0
+ ; CHECK-NEXT: [[LI1:%[0-9]+]]:gprc = LI 1
+ ; CHECK-NEXT: [[XXLXORz:%[0-9]+]]:vsrc = XXLXORz
+ ; CHECK-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 %stack.0, 0
+ ; CHECK-NEXT: [[CMPLWI:%[0-9]+]]:crrc = CMPLWI [[LI]], 0
+ ; CHECK-NEXT: STXVD2X [[XXLXORz]], $zero8, [[ADDI8_]] :: (store (s128) into %stack.0)
+ ; CHECK-NEXT: [[LXVD2X:%[0-9]+]]:vsrc = LXVD2X $zero8, [[ADDI8_]] :: (load (s128) from %stack.0)
+ ; CHECK-NEXT: [[XXPERMDI:%[0-9]+]]:vsrc = XXPERMDI [[LXVD2X]], [[LXVD2X]], 2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrrc = COPY [[XXPERMDI]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vsrc = COPY [[LXVD2X]]
+ ; CHECK-NEXT: [[LI2:%[0-9]+]]:gprc_and_gprc_nor0 = LI 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY [[LI2]]
%7:gprc = LI 0
%8:gprc = LI 1
%21:vsrc = XXLXORz
@@ -67,17 +83,4 @@ body: |
%3:gprc_and_gprc_nor0 = LI 0
%4:gprc = ISEL %3, %8, %29.sub_eq
- ; CHECK-LABEL: name: test_swap_isel_livevars
- ; CHECK: %3:gprc = LI 0
- ; CHECK-NEXT: %4:gprc = LI 1
- ; CHECK-NEXT: %5:vsrc = XXLXORz
- ; CHECK-NEXT: %6:g8rc_and_g8rc_nox0 = ADDI8 %stack.0, 0
- ; CHECK-NEXT: %9:crrc = CMPLWI killed %3, 0
- ; CHECK-NEXT: STXVD2X killed %5, $zero8, %6
- ; CHECK-NEXT: %7:vsrc = LXVD2X $zero8, killed %6
- ; CHECK-NEXT: %8:vsrc = XXPERMDI %7, %7, 2
- ; CHECK-NEXT: %0:vrrc = COPY killed %8
- ; CHECK-NEXT: %10:vsrc = COPY killed %7
- ; CHECK-NEXT: %1:gprc_and_gprc_nor0 = LI 0
- ; CHECK-NEXT: %2:gprc = COPY killed %1
...
diff --git a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
index 739bad616610c..93cfe8f92a41e 100644
--- a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
@@ -11,32 +11,32 @@ body: |
; CHECK-NEXT: successors: %bb.1, %bb.2
; CHECK-NEXT: liveins: $x3, $x4, $x5, $x6
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x6
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY killed $x5
- ; CHECK-NEXT: dead %2:g8rc = COPY killed $x4
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
- ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY1]], 1, implicit-def dead $cr0, implicit-def $cr0gt
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:crbitrc = COPY killed $cr0gt
- ; CHECK-NEXT: BCn killed [[COPY3]], %bb.2
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x6
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY $x5
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc = COPY $x4
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec [[COPY1]], 1, implicit-def $cr0
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
+ ; CHECK-NEXT: BCn killed [[COPY4]], %bb.2
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: liveins: $x3
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[EXTSW:%[0-9]+]]:g8rc = EXTSW killed $x3
- ; CHECK-NEXT: [[RLDICR:%[0-9]+]]:g8rc = RLDICR killed [[ANDI8_rec]], 2, 61
- ; CHECK-NEXT: dead $x3 = COPY killed [[RLDICR]]
- ; CHECK-NEXT: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR killed [[EXTSW]], 2, 61
- ; CHECK-NEXT: [[ADD8_:%[0-9]+]]:g8rc = ADD8 killed [[COPY2]], killed [[RLDICR1]]
- ; CHECK-NEXT: $x3 = COPY killed [[ADD8_]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
+ ; CHECK-NEXT: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec]], 2, 61
+ ; CHECK-NEXT: $x3 = COPY [[RLDICR]]
+ ; CHECK-NEXT: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
+ ; CHECK-NEXT: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
+ ; CHECK-NEXT: $x3 = COPY [[ADD8_]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG killed [[DEF]], killed [[COPY4]], %subreg.sub_32
- ; CHECK-NEXT: $x3 = COPY killed [[INSERT_SUBREG]]
- ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
+ ; CHECK-NEXT: $x3 = COPY [[INSERT_SUBREG]]
+ ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.0.entry:
successors: %bb.1, %bb.2
liveins: $x3, $x4, $x5, $x6
diff --git a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
index d0bcaef75ebef..54c88f5868212 100644
--- a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
+++ b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
@@ -122,7 +122,8 @@ body: |
%3:gprc = LI -11
%4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
; CHECK: LI 4055
- ; CHECK: ANDI_rec killed %3, 4055
+ ; CHECK: ANDI_rec %3, 4055, implicit-def $cr0
+
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rlwinm.
%5:crrc = COPY killed $cr0
@@ -297,7 +298,8 @@ body: |
%0:g8rc = LI8 -11
%2:g8rc_and_g8rc_nox0 = RLDICL_rec %0, 2, 49, implicit-def $cr0
; CHECK: LI8 32727
- ; CHECK: ANDI8_rec killed %0, 32727
+ ; CHECK: ANDI8_rec %0, 32727, implicit-def $cr0
+
; CHECK-LATE-NOT: andi.
; CHECK-LATE: rldicl.
%3:crrc = COPY killed $cr0
diff --git a/llvm/test/CodeGen/PowerPC/sext_elimination.mir b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
index bf6b9005fcf7f..8c88c8f1b06f3 100644
--- a/llvm/test/CodeGen/PowerPC/sext_elimination.mir
+++ b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -run-pass ppc-mi-peepholes -ppc-eliminate-signext -ppc-eliminate-zeroext -verify-machineinstrs -o - %s | FileCheck %s
--- |
@@ -7,7 +8,7 @@
entry:
ret ptr %a
}
-
+
...
---
name: func
@@ -37,20 +38,33 @@ body: |
bb.0.entry:
liveins: $x3
- ; CHECK-LABEL: bb.0.entry:
- ; CHECK: %4:g8rc = EXTSW_32_64 killed %3
- ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
- ; CHECK: %7:g8rc = EXTSW_32_64 killed %6
- ; CHECK: %17:g8rc = INSERT_SUBREG %16, %1, %subreg.sub_32
- ; CHECK-NEXT: %18:g8rc = ORIS8 killed %17, 32767
- ; CHECK-NEXT: %8:gprc = COPY killed %18.sub_32
- ; CHECK: %9:g8rc = INSERT_SUBREG %19, %8, %subreg.sub_32
- ; CHECK: %21:g8rc = INSERT_SUBREG %20, %1, %subreg.sub_32
- ; CHECK-NEXT: %22:g8rc = ORI8 killed %21, 32768
- ; CHECK-NEXT: %10:gprc = COPY killed %22.sub_32
- ; CHECK: %11:g8rc = INSERT_SUBREG %23, %10, %subreg.sub_32
- ; CHECK: %14:g8rc = COPY killed %13
+ ; CHECK-LABEL: name: func
+ ; CHECK: liveins: $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc_nox0 = COPY $x3
+ ; CHECK-NEXT: [[LBZU:%[0-9]+]]:gprc, [[LBZU1:%[0-9]+]]:g8rc_nox0 = LBZU 0, [[COPY]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY [[LBZU1]]
+ ; CHECK-NEXT: [[EXTSW_32_64_:%[0-9]+]]:g8rc = EXTSW_32_64 [[COPY1]]
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[LBZU]], %subreg.sub_32
+ ; CHECK-NEXT: [[ORIS:%[0-9]+]]:gprc = ORIS [[LBZU]], 32768
+ ; CHECK-NEXT: [[EXTSW_32_64_1:%[0-9]+]]:g8rc = EXTSW_32_64 [[ORIS]]
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF1]], [[LBZU]], %subreg.sub_32
+ ; CHECK-NEXT: [[ORIS8_:%[0-9]+]]:g8rc = ORIS8 killed [[INSERT_SUBREG1]], 32767
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY killed [[ORIS8_]].sub_32
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF2]], [[COPY2]], %subreg.sub_32
+ ; CHECK-NEXT: [[DEF3:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF3]], [[LBZU]], %subreg.sub_32
+ ; CHECK-NEXT: [[ORI8_:%[0-9]+]]:g8rc = ORI8 killed [[INSERT_SUBREG3]], 32768
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY killed [[ORI8_]].sub_32
+ ; CHECK-NEXT: [[DEF4:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF4]], [[COPY3]], %subreg.sub_32
+ ; CHECK-NEXT: [[DEF5:%[0-9]+]]:g8rc = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF5]], [[LBZU]], %subreg.sub_32
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:g8rc = COPY [[INSERT_SUBREG5]]
%0:g8rc_nox0 = COPY $x3
%1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
%3:gprc = COPY %2:g8rc_nox0
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