[llvm] [NFC][CostModel][X86] Add cost tests for vXi1 mask broadcasts (PR #225070)
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Mon Sep 21 04:51:23 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-analysis
@llvm/pr-subscribers-backend-x86
Author: Dmitry Sidorov (MrSidims)
<details>
<summary>Changes</summary>
---
Patch is 73.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225070.diff
3 Files Affected:
- (modified) llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll (+75-3)
- (added) llvm/test/Analysis/CostModel/X86/shuffle-mask-broadcast.ll (+75)
- (modified) llvm/test/Analysis/CostModel/X86/shuffle-splat.ll (+183-3)
``````````diff
diff --git a/llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll b/llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
index 7bfab69063d55..6bef388ead5fb 100644
--- a/llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
+++ b/llvm/test/Analysis/CostModel/X86/shuffle-broadcast.ll
@@ -4,9 +4,10 @@
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+sse4.2 | FileCheck %s -check-prefixes=SSE,SSE42
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx | FileCheck %s -check-prefixes=AVX1
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx2 | FileCheck %s -check-prefixes=AVX2
-; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512vbmi | FileCheck %s --check-prefixes=AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512vbmi | FileCheck %s --check-prefixes=AVX512,AVX512VBMI
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512DQ
;
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mcpu=slm | FileCheck %s --check-prefixes=SSE,SSE42
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mcpu=goldmont | FileCheck %s --check-prefixes=SSE,SSE42
@@ -464,3 +465,74 @@ define void @test_upper_vXf32(<2 x float> %a64, <2 x float> %b64, <4 x float> %a
%V512 = shufflevector <16 x float> %a512, <16 x float> %b512, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret void
}
+
+define void @test_load_vXi1(ptr %p16, ptr %p64) {
+; SSE2-LABEL: 'test_load_vXi1'
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:3 SizeLat:4 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; SSE2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:3 SizeLat:4 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; SSSE3-LABEL: 'test_load_vXi1'
+; SSSE3-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; SSSE3-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:3 SizeLat:2 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; SSSE3-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; SSSE3-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:3 SizeLat:2 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; SSSE3-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; SSE42-LABEL: 'test_load_vXi1'
+; SSE42-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; SSE42-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:3 SizeLat:2 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; SSE42-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; SSE42-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:3 SizeLat:2 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; SSE42-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; AVX1-LABEL: 'test_load_vXi1'
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:3 SizeLat:2 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:3 Lat:4 SizeLat:6 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; AVX2-LABEL: 'test_load_vXi1'
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; AVX2-NEXT: Cost Model: Found costs of 0 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; AVX2-NEXT: Cost Model: Found costs of 0 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; AVX512F-LABEL: 'test_load_vXi1'
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; AVX512F-NEXT: Cost Model: Found costs of 0 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; AVX512F-NEXT: Cost Model: Found costs of 0 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; AVX512BW-LABEL: 'test_load_vXi1'
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; AVX512BW-NEXT: Cost Model: Found costs of 0 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; AVX512BW-NEXT: Cost Model: Found costs of 0 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; AVX512VBMI-LABEL: 'test_load_vXi1'
+; AVX512VBMI-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; AVX512VBMI-NEXT: Cost Model: Found costs of 0 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; AVX512VBMI-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; AVX512VBMI-NEXT: Cost Model: Found costs of 0 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; AVX512VBMI-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+; AVX512DQ-LABEL: 'test_load_vXi1'
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:4 SizeLat:1 for: %src16 = load <16 x i1>, ptr %p16, align 2
+; AVX512DQ-NEXT: Cost Model: Found costs of 0 for: %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %src64 = load <64 x i1>, ptr %p64, align 8
+; AVX512DQ-NEXT: Cost Model: Found costs of 0 for: %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+; AVX512DQ-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
+;
+ %src16 = load <16 x i1>, ptr %p16
+ %V16 = shufflevector <16 x i1> %src16, <16 x i1> poison, <16 x i32> zeroinitializer
+ %src64 = load <64 x i1>, ptr %p64
+ %V64 = shufflevector <64 x i1> %src64, <64 x i1> poison, <64 x i32> zeroinitializer
+ ret void
+}
diff --git a/llvm/test/Analysis/CostModel/X86/shuffle-mask-broadcast.ll b/llvm/test/Analysis/CostModel/X86/shuffle-mask-broadcast.ll
new file mode 100644
index 0000000000000..8b33d75e662ae
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/shuffle-mask-broadcast.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl,+fast-variable-crosslane-shuffle | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512vl,+fast-variable-crosslane-shuffle | FileCheck %s --check-prefixes=CHECK,X64-NODQ
+; RUN: opt < %s -mtriple=i386-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl,+fast-variable-crosslane-shuffle | FileCheck %s --check-prefixes=CHECK,X86
+
+define <16 x i1> @lane16_bw_0(<16 x i1> %src) #0 {
+; CHECK-LABEL: 'lane16_bw_0'
+; CHECK-NEXT: Cost Model: Found costs of 17 for: %s = shufflevector <16 x i1> %src, <16 x i1> poison, <16 x i32> zeroinitializer
+; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <16 x i1> %s
+;
+ %s = shufflevector <16 x i1> %src, <16 x i1> poison, <16 x i32> splat (i32 0)
+ ret <16 x i1> %s
+}
+
+define <16 x i1> @lane16_bw_1(<16 x i1> %src) #0 {
+; CHECK-LABEL: 'lane16_bw_1'
+; CHECK-NEXT: Cost Model: Found costs of 17 for: %s = shufflevector <16 x i1> %src, <16 x i1> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <16 x i1> %s
+;
+ %s = shufflevector <16 x i1> %src, <16 x i1> poison, <16 x i32> splat (i32 1)
+ ret <16 x i1> %s
+}
+
+define <16 x i1> @lane16_dword_0(<16 x i1> %src) #1 {
+; CHECK-LABEL: 'lane16_dword_0'
+; CHECK-NEXT: Cost Model: Found costs of 17 for: %s = shufflevector <16 x i1> %src, <16 x i1> poison, <16 x i32> zeroinitializer
+; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <16 x i1> %s
+;
+ %s = shufflevector <16 x i1> %src, <16 x i1> poison, <16 x i32> splat (i32 0)
+ ret <16 x i1> %s
+}
+
+define <64 x i1> @lane64_no512_0(<64 x i1> %src) #2 {
+; CHECK-LABEL: 'lane64_no512_0'
+; CHECK-NEXT: Cost Model: Found costs of 65 for: %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> zeroinitializer
+; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <64 x i1> %s
+;
+ %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> splat (i32 0)
+ ret <64 x i1> %s
+}
+
+define <64 x i1> @lane64_no512_17(<64 x i1> %src) #2 {
+; CHECK-LABEL: 'lane64_no512_17'
+; CHECK-NEXT: Cost Model: Found costs of 65 for: %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <64 x i1> %s
+;
+ %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> splat (i32 17)
+ ret <64 x i1> %s
+}
+
+define <64 x i1> @lane64_512_0(<64 x i1> %src) #0 {
+; CHECK-LABEL: 'lane64_512_0'
+; CHECK-NEXT: Cost Model: Found costs of 65 for: %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> zeroinitializer
+; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <64 x i1> %s
+;
+ %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> splat (i32 0)
+ ret <64 x i1> %s
+}
+
+define <64 x i1> @lane64_512_17(<64 x i1> %src) #0 {
+; CHECK-LABEL: 'lane64_512_17'
+; CHECK-NEXT: Cost Model: Found costs of 65 for: %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <64 x i1> %s
+;
+ %s = shufflevector <64 x i1> %src, <64 x i1> poison, <64 x i32> splat (i32 17)
+ ret <64 x i1> %s
+}
+
+attributes #0 = { "prefer-vector-width"="256" "min-legal-vector-width"="512" }
+attributes #1 = { "prefer-vector-width"="512" "min-legal-vector-width"="512" }
+attributes #2 = { "prefer-vector-width"="256" "min-legal-vector-width"="0" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; X64: {{.*}}
+; X64-NODQ: {{.*}}
+; X86: {{.*}}
diff --git a/llvm/test/Analysis/CostModel/X86/shuffle-splat.ll b/llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
index b3cc220c0f3c3..70498a3ee0d8f 100644
--- a/llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
+++ b/llvm/test/Analysis/CostModel/X86/shuffle-splat.ll
@@ -4,9 +4,12 @@
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+sse4.2 | FileCheck %s -check-prefixes=SSE,SSE42
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx | FileCheck %s -check-prefixes=AVX1
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx2 | FileCheck %s -check-prefixes=AVX2
-; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512vbmi | FileCheck %s --check-prefixes=AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512vbmi | FileCheck %s --check-prefixes=AVX512,AVX512VBMI
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512DQ
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl,+fast-variable-crosslane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512DQ-FAST
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mattr=+avx512f,+avx512bw,+avx512vbmi,+fast-variable-crosslane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512VBMI-FAST
;
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mcpu=slm | FileCheck %s --check-prefixes=SSE,SSE42
; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=all -mcpu=goldmont | FileCheck %s --check-prefixes=SSE,SSE42
@@ -425,6 +428,126 @@ define void @test_vXi1(<2 x i1> %src2, <4 x i1> %src4, <8 x i1> %src8, <16 x i1>
ret void
}
+;
+; Verify the cost model for splat shuffles of masks wider than one legal mask
+; register. The first lane of every part is a plain splat, any other lane is
+; not.
+;
+
+define void @test_multireg_vXi1(<128 x i1> %src128) {
+; SSE2-LABEL: 'test_multireg_vXi1'
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:3 SizeLat:4 for: %V0 = shufflevector <128 x i1> %src128, <128 x i1> poison, <128 x i32> zeroinitializer
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:3 SizeLat:4 for: %V64 = shufflevector <128 x i1> %src128, <128 x i1> poison, <128 x i32> <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
+; SSE2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:3 SizeLat:4 for: %V65 = shufflevector <128 x i1> %src128, <128 x i1> poison, <128 x i32> <i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65, i32 65...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/225070
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