[llvm] [ExpandReductions] Add support for non-pow2 vector counts (PR #208738)
Prajwal KP via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 21 02:46:14 PDT 2026
https://github.com/Prajwal-kp-18 updated https://github.com/llvm/llvm-project/pull/208738
>From c2bbff2f6ea66a3454546c186d7e07c793189238 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Fri, 10 Jul 2026 19:52:57 +0530
Subject: [PATCH 1/2] [CodeGen] Expand non-pow2 vector reductions by
scalarizing
---
llvm/lib/CodeGen/ExpandReductions.cpp | 46 +++-
llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll | 155 ++++-------
llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll | 96 +++----
llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll | 149 +++++------
llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll | 63 ++---
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 157 ++++-------
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 157 ++++-------
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 124 +++------
.../test/CodeGen/AMDGPU/vector-reduce-umin.ll | 126 +++------
llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll | 80 +++---
.../Generic/expand-experimental-reductions.ll | 6 +-
.../RISCV/rvv/fixed-vectors-reduction-int.ll | 19 +-
.../test/CodeGen/RISCV/rvv/vreductions-int.ll | 246 +++++++++++-------
.../llvm-vector-reduce/add.ll | 30 +--
.../llvm-vector-reduce/and.ll | 30 +--
.../llvm-vector-reduce/mul.ll | 30 +--
.../llvm-vector-reduce/or.ll | 30 +--
.../llvm-vector-reduce/smax.ll | 30 +--
.../llvm-vector-reduce/smin.ll | 30 +--
.../llvm-vector-reduce/umax.ll | 30 +--
.../llvm-vector-reduce/umin.ll | 30 +--
.../llvm-vector-reduce/xor.ll | 30 +--
.../llvm-intrinsics/llvm-vector-reduce/add.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/and.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/mul.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/or.ll | 8 +-
.../llvm-vector-reduce/smax.ll | 8 +-
.../llvm-vector-reduce/smin.ll | 8 +-
.../llvm-vector-reduce/umax.ll | 8 +-
.../llvm-vector-reduce/umin.ll | 8 +-
.../llvm-intrinsics/llvm-vector-reduce/xor.ll | 8 +-
.../WebAssembly/simd-vecreduce-bool.ll | 4 +-
.../CodeGen/X86/vector-reduce-fmax-nnan.ll | 24 +-
.../X86/x86-partial-reduction-byte-sum.ll | 192 +++++++++++++-
34 files changed, 937 insertions(+), 1049 deletions(-)
diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp
index 1cc4d16c95546..bead77c1a07d6 100644
--- a/llvm/lib/CodeGen/ExpandReductions.cpp
+++ b/llvm/lib/CodeGen/ExpandReductions.cpp
@@ -28,6 +28,21 @@ using namespace llvm;
namespace {
+Value *expandScalarizedReduction(IRBuilderBase &Builder, Value *Vec,
+ unsigned RdxOpcode, RecurKind RK) {
+ auto *VecTy = cast<FixedVectorType>(Vec->getType());
+ Value *Res = Builder.CreateExtractElement(Vec, uint64_t(0));
+ for (unsigned I = 1, E = VecTy->getNumElements(); I != E; ++I) {
+ Value *Ext = Builder.CreateExtractElement(Vec, I);
+ if (RdxOpcode == Instruction::ICmp || RdxOpcode == Instruction::FCmp)
+ Res = createMinMaxOp(Builder, RK, Res, Ext);
+ else
+ Res = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, Res, Ext,
+ "bin.rdx");
+ }
+ return Res;
+}
+
bool expandReductions(Function &F, const TargetTransformInfo *TTI,
DominatorTree *DT, LoopInfo *LI) {
bool Changed = false;
@@ -88,12 +103,11 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
Rdx = expandReductionViaLoop(Builder, Vec, RdxOpcode, Acc, DT, LI);
break;
}
- if (!FMF.allowReassoc())
+ if (!FMF.allowReassoc() ||
+ !isPowerOf2_32(
+ cast<FixedVectorType>(Vec->getType())->getNumElements()))
Rdx = getOrderedReduction(Builder, Acc, Vec, RdxOpcode, RK);
else {
- if (!isPowerOf2_32(
- cast<FixedVectorType>(Vec->getType())->getNumElements()))
- continue;
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
Rdx = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, Acc, Rdx,
"bin.rdx");
@@ -112,10 +126,9 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
Value *Vec = II->getArgOperand(0);
auto *FTy = cast<FixedVectorType>(Vec->getType());
unsigned NumElts = FTy->getNumElements();
- if (!isPowerOf2_32(NumElts))
- continue;
- if (FTy->getElementType() == Builder.getInt1Ty()) {
+ if (FTy->getElementType() == Builder.getInt1Ty() &&
+ isPowerOf2_32(NumElts)) {
Rdx = Builder.CreateBitCast(Vec, Builder.getIntNTy(NumElts));
if (ID == Intrinsic::vector_reduce_and) {
Rdx = Builder.CreateICmpEQ(
@@ -127,6 +140,10 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
break;
}
unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+ if (!isPowerOf2_32(NumElts)) {
+ Rdx = expandScalarizedReduction(Builder, Vec, RdxOpcode, RK);
+ break;
+ }
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
break;
}
@@ -146,8 +163,10 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
break;
}
if (!isPowerOf2_32(
- cast<FixedVectorType>(Vec->getType())->getNumElements()))
- continue;
+ cast<FixedVectorType>(Vec->getType())->getNumElements())) {
+ Rdx = expandScalarizedReduction(Builder, Vec, RdxOpcode, RK);
+ break;
+ }
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
break;
}
@@ -156,11 +175,14 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
// We require "nnan" to use a shuffle reduction; "nsz" is implied by the
// semantics of the reduction.
Value *Vec = II->getArgOperand(0);
- if (!isPowerOf2_32(
- cast<FixedVectorType>(Vec->getType())->getNumElements()) ||
- !FMF.noNaNs())
+ if (!FMF.noNaNs())
continue;
unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+ if (!isPowerOf2_32(
+ cast<FixedVectorType>(Vec->getType())->getNumElements())) {
+ Rdx = expandScalarizedReduction(Builder, Vec, RdxOpcode, RK);
+ break;
+ }
Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RS, RK);
break;
}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
index 5da1363b30397..fa1828636668d 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
@@ -110,76 +110,48 @@ entry:
}
define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX7-GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_add_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_add_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u16_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: test_vector_reduce_add_v3i8:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_add_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_add_v3i8:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_add_v3i8:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i8:
@@ -205,9 +177,9 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i8:
@@ -217,9 +189,9 @@ define i8 @test_vector_reduce_add_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i8:
@@ -1294,10 +1266,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_add_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_add_v3i16:
@@ -1315,52 +1286,36 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_add_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_pk_add_u16 v1, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_add_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_add_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_add_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_add_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-SDAG-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_add_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_add_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_add_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_add_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX10-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v1, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i16:
@@ -1387,9 +1342,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v1, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
@@ -1400,9 +1355,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_add_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
index 7bd805dd8c575..a8c508af1cbe3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
@@ -161,76 +161,48 @@ entry:
}
define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_and_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_and_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: test_vector_reduce_and_v3i8:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_and_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_and_v3i8:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_and_v3i8:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_and_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_and_v3i8:
@@ -248,9 +220,9 @@ define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_and_v3i8:
@@ -260,9 +232,9 @@ define i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_and_v3i8:
@@ -1068,9 +1040,9 @@ define i16 @test_vector_reduce_and_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_and_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_and_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
index ea563e99ba6e2..5a3de55451aa9 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
@@ -175,8 +175,12 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_mul_v3i8:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_mul_v3i8:
@@ -186,62 +190,41 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_mul_lo_u32 v0, v0, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v1, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_mul_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_mul_lo_u16_e32 v0, v1, v0
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_mul_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_mul_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-SDAG-LABEL: test_vector_reduce_mul_v3i8:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_mul_lo_u16 v0, v1, v0
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_mul_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_mul_v3i8:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_mul_v3i8:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v1, v0
+; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
@@ -267,9 +250,9 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i8:
@@ -279,9 +262,9 @@ define i8 @test_vector_reduce_mul_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v1, v0
+; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i8:
@@ -1232,12 +1215,12 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_mul_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_or_b32_e32 v1, 0x10000, v1
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v1, v0, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, 1, v0
-; GFX7-SDAG-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX7-SDAG-NEXT: v_mul_u32_u24_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_mul_v3i16:
@@ -1255,52 +1238,36 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_mul_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_pk_mul_lo_u16 v1, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_mul_lo_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_mul_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mul_lo_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-GISEL-NEXT: v_mul_lo_u16_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_mul_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-SDAG-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_mul_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_mul_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-GISEL-NEXT: v_mul_lo_u16 v0, v0, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_mul_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
@@ -1327,9 +1294,9 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
@@ -1340,9 +1307,9 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-FAKE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_mul_lo_u16 v0, v0, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
index d7db9c845b4ad..f0896f23a980c 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
@@ -161,39 +161,25 @@ entry:
}
define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_or_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_or_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_or_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_or_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-GISEL-LABEL: test_vector_reduce_or_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_or_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_or_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -205,8 +191,8 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX10-SDAG-LABEL: test_vector_reduce_or_v3i8:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -218,17 +204,17 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_or_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -244,9 +230,9 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_or_v3i8:
@@ -256,9 +242,9 @@ define i8 @test_vector_reduce_or_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_or_v3i8:
@@ -1098,10 +1084,9 @@ define i16 @test_vector_reduce_or_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_or_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_or_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 659882d67d6c8..25b64d2aaf23a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -137,11 +137,9 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-SDAG-NEXT: v_max_i32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0xff80
-; GFX7-SDAG-NEXT: v_max3_i32 v0, v1, v0, s4
+; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-SDAG-NEXT: v_max3_i32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -153,28 +151,20 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_max3_i32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_smax_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_max_i16_sdwa v0, sext(v1), v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_max_i16_e32 v0, 0xff80, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_smax_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_max_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_smax_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_max_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX9-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX9-SDAG-NEXT: v_max_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0xff80
-; GFX9-SDAG-NEXT: v_max3_i16 v0, v1, v0, s0
+; GFX9-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-SDAG-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -190,10 +180,9 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-SDAG-NEXT: v_max_i16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_max3_i16 v0, v1, v0, 0xff80
+; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX10-SDAG-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -208,28 +197,21 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v0.l, 0xff80
+; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_max3_i16 v0, v1, v0, 0xff80
+; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -249,17 +231,11 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v0.l, 0xff80
+; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i8:
@@ -270,11 +246,10 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: v_max3_i16 v0, v1, v0, 0xff80
+; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smax_v3i8:
@@ -1690,12 +1665,10 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_smax_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v2, 16, v0
+; GFX7-SDAG-NEXT: v_bfe_i32 v2, v0, 0, 16
+; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX7-SDAG-NEXT: v_max_i32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX7-SDAG-NEXT: v_max3_i32 v0, v0, v2, s4
+; GFX7-SDAG-NEXT: v_max3_i32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smax_v3i16:
@@ -1714,60 +1687,32 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_max_i16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_smax_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0x8000
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v1, s0, v1, v2
-; GFX9-SDAG-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_max_i16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_smax_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_smax_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
-; GFX10-SDAG-NEXT: v_perm_b32 v1, s4, v1, 0x5040100
-; GFX10-SDAG-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_max_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_smax_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_smax_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_max3_i16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_smax_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_max3_i16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v0.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smax_v3i16:
@@ -1785,10 +1730,7 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x8000
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v0.h, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
@@ -1798,14 +1740,9 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_max3_i16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smax_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 09f08d332793e..9f52f405085c5 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -137,11 +137,9 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX7-SDAG-NEXT: v_min_i32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0x7f
-; GFX7-SDAG-NEXT: v_min3_i32 v0, v1, v0, s4
+; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-SDAG-NEXT: v_min3_i32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -153,28 +151,20 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_min3_i32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_smin_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_min_i16_sdwa v0, sext(v1), v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_min_i16_e32 v0, 0x7f, v0
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_smin_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_min_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_smin_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_min_i16_sdwa v0, v0, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX9-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX9-SDAG-NEXT: v_min_i16_sdwa v0, sext(v0), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0x7f
-; GFX9-SDAG-NEXT: v_min3_i16 v0, v1, v0, s0
+; GFX9-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX9-SDAG-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -190,10 +180,9 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX10-SDAG-NEXT: v_min_i16 v0, v0, v2
-; GFX10-SDAG-NEXT: v_min3_i16 v0, v1, v0, 0x7f
+; GFX10-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX10-SDAG-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -208,28 +197,21 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v0.l, 0x7f
+; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v1.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: v_min3_i16 v0, v1, v0, 0x7f
+; GFX11-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -249,17 +231,11 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v0.l, 0x7f
+; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v1.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i8:
@@ -270,11 +246,10 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: v_min3_i16 v0, v1, v0, 0x7f
+; GFX12-SDAG-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smin_v3i8:
@@ -1690,12 +1665,10 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_smin_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v2, 16, v0
+; GFX7-SDAG-NEXT: v_bfe_i32 v2, v0, 0, 16
+; GFX7-SDAG-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX7-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX7-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX7-SDAG-NEXT: v_min_i32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_movk_i32 s4, 0x7fff
-; GFX7-SDAG-NEXT: v_min3_i32 v0, v0, v2, s4
+; GFX7-SDAG-NEXT: v_min3_i32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_smin_v3i16:
@@ -1714,60 +1687,32 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_min_i16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_smin_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_movk_i32 s0, 0x7fff
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v1, s0, v1, v2
-; GFX9-SDAG-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_min_i16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_smin_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_smin_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x7fff
-; GFX10-SDAG-NEXT: v_perm_b32 v1, s4, v1, 0x5040100
-; GFX10-SDAG-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_min_i16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_smin_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_smin_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_min3_i16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_smin_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_min3_i16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v0.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7fff
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_smin_v3i16:
@@ -1785,10 +1730,7 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7fff
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v0.h, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
@@ -1798,14 +1740,9 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: s_movk_i32 s0, 0x7fff
-; GFX12-SDAG-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, s0, v1, 0x5040100
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min_i16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_min3_i16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_smin_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 2a587008515e5..9a99c1490dd1b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -137,9 +137,9 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-SDAG-NEXT: v_max3_u32 v0, v1, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_max3_u32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -151,27 +151,20 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_umax_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_max_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_umax_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_max_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_umax_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_max_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_max_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX9-SDAG-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-SDAG-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -187,9 +180,9 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-SDAG-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-SDAG-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -205,20 +198,20 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -239,10 +232,10 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i8:
@@ -253,10 +246,10 @@ define i8 @test_vector_reduce_umax_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max3_u16 v0, v1, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umax_v3i8:
@@ -1579,20 +1572,19 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_umax_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7-SDAG-NEXT: v_max_u32_e32 v1, v2, v1
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX7-SDAG-NEXT: v_max3_u32 v0, v1, v0, 0
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-SDAG-NEXT: v_max3_u32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umax_v3i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7-GISEL-NEXT: v_bfe_u32 v0, v0, 16, 16
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_max3_u32 v0, v2, v0, v1
+; GFX7-GISEL-NEXT: v_max3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_umax_v3i16:
@@ -1602,56 +1594,32 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_max_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_umax_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-SDAG-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_max_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_umax_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_umax_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX10-SDAG-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_max_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_umax_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_umax_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_max3_u16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_umax_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_max3_u16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v0.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_max_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umax_v3i16:
@@ -1669,10 +1637,7 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_max3_u16 v0.l, v0.l, v0.h, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
@@ -1682,12 +1647,9 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_max_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_max3_u16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umax_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 77ea7b6d8df87..9b6ff9a57442f 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -137,9 +137,9 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX7-SDAG-NEXT: v_min3_u32 v0, v1, v0, v2
+; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-SDAG-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -151,27 +151,20 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v1, v2
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-SDAG-LABEL: test_vector_reduce_umin_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-SDAG-NEXT: v_min_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_umin_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_min_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_umin_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_min_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
+; GFX8-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umin_v3i8:
; GFX9-SDAG: ; %bb.0: ; %entry
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX9-SDAG-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-SDAG-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -187,9 +180,9 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-SDAG-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX10-SDAG-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX10-SDAG-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -205,20 +198,20 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX11-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -239,10 +232,10 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v1.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i8:
@@ -253,10 +246,10 @@ define i8 @test_vector_reduce_umin_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min3_u16 v0, v1, v0, v2
+; GFX12-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v1, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umin_v3i8:
@@ -1359,21 +1352,19 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_umin_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-SDAG-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7-SDAG-NEXT: s_mov_b32 s4, 0xffff
-; GFX7-SDAG-NEXT: v_min_u32_e32 v1, v2, v1
; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX7-SDAG-NEXT: v_min3_u32 v0, v1, v0, s4
+; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX7-SDAG-NEXT: v_min3_u32 v0, v2, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_umin_v3i16:
; GFX7-GISEL: ; %bb.0: ; %entry
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX7-GISEL-NEXT: v_bfe_u32 v0, v0, 16, 16
+; GFX7-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX7-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-GISEL-NEXT: v_min3_u32 v0, v2, v0, v1
+; GFX7-GISEL-NEXT: v_min3_u32 v0, v0, v2, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_vector_reduce_umin_v3i16:
@@ -1383,57 +1374,32 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX8-NEXT: v_min_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_umin_v3i16:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x5040100
-; GFX9-SDAG-NEXT: v_perm_b32 v1, -1, v1, v2
-; GFX9-SDAG-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX9-SDAG-NEXT: s_nop 0
-; GFX9-SDAG-NEXT: v_min_u16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-GISEL-LABEL: test_vector_reduce_umin_v3i16:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX9-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX10-SDAG-LABEL: test_vector_reduce_umin_v3i16:
-; GFX10-SDAG: ; %bb.0: ; %entry
-; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_perm_b32 v1, -1, v1, 0x5040100
-; GFX10-SDAG-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-SDAG-NEXT: v_min_u16 v0, v0, v1
-; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_umin_v3i16:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX9-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-GISEL-LABEL: test_vector_reduce_umin_v3i16:
-; GFX10-GISEL: ; %bb.0: ; %entry
-; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX10-GISEL-NEXT: v_min3_u16 v0, v0, v2, v1
-; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: test_vector_reduce_umin_v3i16:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_min3_u16 v0, v0, v2, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, -1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v0.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_perm_b32 v1, -1, v1, 0x5040100
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-FAKE16-NEXT: v_min_u16 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_umin_v3i16:
@@ -1451,10 +1417,7 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, -1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_min3_u16 v0.l, v0.l, v0.h, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
@@ -1464,12 +1427,9 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_perm_b32 v1, -1, v1, 0x5040100
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-FAKE16-NEXT: v_min_u16 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: v_min3_u16 v0, v0, v2, v1
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_umin_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
index b68654a2f9ff4..f8098f7be5ce4 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
@@ -161,53 +161,32 @@ entry:
}
define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
-; GFX7-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX7-SDAG: ; %bb.0: ; %entry
-; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX7-GISEL-LABEL: test_vector_reduce_xor_v3i8:
-; GFX7-GISEL: ; %bb.0: ; %entry
-; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX7-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX8-SDAG: ; %bb.0: ; %entry
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX8-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: test_vector_reduce_xor_v3i8:
-; GFX8-GISEL: ; %bb.0: ; %entry
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: test_vector_reduce_xor_v3i8:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-SDAG-LABEL: test_vector_reduce_xor_v3i8:
-; GFX9-SDAG: ; %bb.0: ; %entry
-; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX9-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+; GFX8-LABEL: test_vector_reduce_xor_v3i8:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-GISEL-LABEL: test_vector_reduce_xor_v3i8:
-; GFX9-GISEL: ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1
-; GFX9-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_vector_reduce_xor_v3i8:
+; GFX9: ; %bb.0: ; %entry
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: test_vector_reduce_xor_v3i8:
; GFX10-SDAG: ; %bb.0: ; %entry
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: test_vector_reduce_xor_v3i8:
@@ -219,17 +198,17 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_xor_v3i8:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i8:
; GFX11-SDAG-FAKE16: ; %bb.0: ; %entry
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: test_vector_reduce_xor_v3i8:
@@ -245,9 +224,9 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_xor_v3i8:
@@ -257,9 +236,9 @@ define i8 @test_vector_reduce_xor_v3i8(<3 x i8> %v) {
; GFX12-SDAG-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-FAKE16-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX12-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: test_vector_reduce_xor_v3i8:
@@ -1045,10 +1024,9 @@ define i16 @test_vector_reduce_xor_v3i16(<3 x i16> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_xor_v3i16:
; GFX7-SDAG: ; %bb.0: ; %entry
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX7-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX7-SDAG-NEXT: v_alignbit_b32 v2, v1, v0, 16
; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX7-SDAG-NEXT: v_xor_b32_e32 v0, v0, v1
; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-GISEL-LABEL: test_vector_reduce_xor_v3i16:
diff --git a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
index 241d98d3d6b9d..130ca02368cff 100644
--- a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
+++ b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
@@ -335,7 +335,11 @@ entry:
define i8 @test_v3i8(<3 x i8> %a) nounwind {
; CHECK-LABEL: @test_v3i8(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[B:%.*]] = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> [[A:%.*]])
+; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i8> [[A:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i8> [[A]], i64 1
+; CHECK-NEXT: [[BIN_RDX:%.*]] = and i8 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i8> [[A]], i64 2
+; CHECK-NEXT: [[B:%.*]] = and i8 [[BIN_RDX]], [[TMP2]]
; CHECK-NEXT: ret i8 [[B]]
;
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
index 4ef25e3ec8fbf..66c1db12d6705 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
@@ -5379,20 +5379,15 @@ define i8 @vreduce_mul_v2i8(ptr %x) {
define i8 @vreduce_mul_v3i8(ptr %x) {
; CHECK-LABEL: vreduce_mul_v3i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 1
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
-; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vslideup.vi v9, v8, 3
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vmul.vv v8, v9, v8
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
+; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: vslidedown.vi v9, v8, 1
+; CHECK-NEXT: vmv.x.s a1, v9
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: vmv.x.s a1, v8
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: ret
%v = load <3 x i8>, ptr %x
%red = call i8 @llvm.vector.reduce.mul.v3i8(<3 x i8> %v)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
index 0c2fee71b45af..f4a1fc4f578a3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
@@ -2420,112 +2420,158 @@ define signext i32 @vreduce_mul_nxv4i32_exact_vlen(<vscale x 4 x i32> %v) vscale
}
define signext i32 @vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen(<vscale x 8 x i32> %v) vscale_range(2,2) {
-; CHECK-LABEL: vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v11, v10, 3
-; CHECK-NEXT: vmv.x.s a0, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vmv.x.s a1, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 1
-; CHECK-NEXT: vmv.x.s a2, v11
-; CHECK-NEXT: vmv.x.s a3, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 3
-; CHECK-NEXT: vmv.x.s a4, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 2
-; CHECK-NEXT: vmv.x.s a5, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vmv.x.s a6, v10
-; CHECK-NEXT: vmv.x.s a7, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 3
-; CHECK-NEXT: vmv.x.s t0, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vmv.x.s t1, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vmv.x.s t2, v8
-; CHECK-NEXT: vmv.x.s t3, v9
-; CHECK-NEXT: vmv.v.x v8, t3
-; CHECK-NEXT: vslide1down.vx v8, v8, t2
-; CHECK-NEXT: vslide1down.vx v8, v8, t1
-; CHECK-NEXT: vslide1down.vx v9, v8, t0
-; CHECK-NEXT: vmv.v.x v8, a7
-; CHECK-NEXT: vmv.v.x v10, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a6
-; CHECK-NEXT: vslide1down.vx v10, v10, a2
-; CHECK-NEXT: vslide1down.vx v8, v8, a5
-; CHECK-NEXT: vslide1down.vx v10, v10, a1
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: vslide1down.vx v10, v10, a0
-; CHECK-NEXT: vmv.v.i v11, 1
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v11, v10, 1
+; RV32-NEXT: vmv.x.s a0, v11
+; RV32-NEXT: vmv.x.s a1, v10
+; RV32-NEXT: vslidedown.vi v11, v9, 3
+; RV32-NEXT: vmv.x.s a2, v11
+; RV32-NEXT: vslidedown.vi v11, v9, 1
+; RV32-NEXT: vmv.x.s a3, v11
+; RV32-NEXT: vmv.x.s a4, v9
+; RV32-NEXT: vslidedown.vi v11, v8, 3
+; RV32-NEXT: vmv.x.s a5, v11
+; RV32-NEXT: vslidedown.vi v11, v8, 2
+; RV32-NEXT: vmv.x.s a6, v11
+; RV32-NEXT: vmv.x.s a7, v8
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s t0, v8
+; RV32-NEXT: vslidedown.vi v8, v9, 2
+; RV32-NEXT: vmv.x.s t1, v8
+; RV32-NEXT: mul a7, a7, t0
+; RV32-NEXT: mul a5, a6, a5
+; RV32-NEXT: mul a3, a4, a3
+; RV32-NEXT: mul a1, a2, a1
+; RV32-NEXT: vslidedown.vi v8, v10, 2
+; RV32-NEXT: vmv.x.s a2, v8
+; RV32-NEXT: mul a4, a7, a5
+; RV32-NEXT: mul a3, a3, t1
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: mul a1, a4, a3
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: vslidedown.vi v8, v10, 3
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: vmv.x.s a1, v8
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v11, v10, 1
+; RV64-NEXT: vmv.x.s a0, v11
+; RV64-NEXT: vmv.x.s a1, v10
+; RV64-NEXT: vslidedown.vi v11, v9, 3
+; RV64-NEXT: vmv.x.s a2, v11
+; RV64-NEXT: vslidedown.vi v11, v9, 1
+; RV64-NEXT: vmv.x.s a3, v11
+; RV64-NEXT: vmv.x.s a4, v9
+; RV64-NEXT: vslidedown.vi v11, v8, 3
+; RV64-NEXT: vmv.x.s a5, v11
+; RV64-NEXT: vslidedown.vi v11, v8, 2
+; RV64-NEXT: vmv.x.s a6, v11
+; RV64-NEXT: vmv.x.s a7, v8
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s t0, v8
+; RV64-NEXT: vslidedown.vi v8, v9, 2
+; RV64-NEXT: vmv.x.s t1, v8
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: mul a5, a6, a5
+; RV64-NEXT: mul a3, a4, a3
+; RV64-NEXT: mul a1, a2, a1
+; RV64-NEXT: vslidedown.vi v8, v10, 2
+; RV64-NEXT: vmv.x.s a2, v8
+; RV64-NEXT: mul a4, a7, a5
+; RV64-NEXT: mul a3, a3, t1
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: mul a1, a4, a3
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: vslidedown.vi v8, v10, 3
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: vmv.x.s a1, v8
+; RV64-NEXT: mulw a0, a0, a1
+; RV64-NEXT: ret
%sub = call <vscale x 6 x i32> @llvm.vector.extract.nxv6i32.nxv8i32(<vscale x 8 x i32> %v, i64 0)
%red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %sub)
ret i32 %red
}
define signext i32 @vreduce_mul_nxv6i32_exact_vlen(<vscale x 6 x i32> %v) vscale_range(2,2) {
-; CHECK-LABEL: vreduce_mul_nxv6i32_exact_vlen:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v11, v10, 3
-; CHECK-NEXT: vmv.x.s a0, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vmv.x.s a1, v11
-; CHECK-NEXT: vslidedown.vi v11, v10, 1
-; CHECK-NEXT: vmv.x.s a2, v11
-; CHECK-NEXT: vmv.x.s a3, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 3
-; CHECK-NEXT: vmv.x.s a4, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 2
-; CHECK-NEXT: vmv.x.s a5, v10
-; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vmv.x.s a6, v10
-; CHECK-NEXT: vmv.x.s a7, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 3
-; CHECK-NEXT: vmv.x.s t0, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vmv.x.s t1, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vmv.x.s t2, v8
-; CHECK-NEXT: vmv.x.s t3, v9
-; CHECK-NEXT: vmv.v.x v8, t3
-; CHECK-NEXT: vslide1down.vx v8, v8, t2
-; CHECK-NEXT: vslide1down.vx v8, v8, t1
-; CHECK-NEXT: vslide1down.vx v9, v8, t0
-; CHECK-NEXT: vmv.v.x v8, a7
-; CHECK-NEXT: vmv.v.x v10, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a6
-; CHECK-NEXT: vslide1down.vx v10, v10, a2
-; CHECK-NEXT: vslide1down.vx v8, v8, a5
-; CHECK-NEXT: vslide1down.vx v10, v10, a1
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: vslide1down.vx v10, v10, a0
-; CHECK-NEXT: vmv.v.i v11, 1
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v9, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: vreduce_mul_nxv6i32_exact_vlen:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v11, v10, 1
+; RV32-NEXT: vmv.x.s a0, v11
+; RV32-NEXT: vmv.x.s a1, v10
+; RV32-NEXT: vslidedown.vi v11, v9, 3
+; RV32-NEXT: vmv.x.s a2, v11
+; RV32-NEXT: vslidedown.vi v11, v9, 1
+; RV32-NEXT: vmv.x.s a3, v11
+; RV32-NEXT: vmv.x.s a4, v9
+; RV32-NEXT: vslidedown.vi v11, v8, 3
+; RV32-NEXT: vmv.x.s a5, v11
+; RV32-NEXT: vslidedown.vi v11, v8, 2
+; RV32-NEXT: vmv.x.s a6, v11
+; RV32-NEXT: vmv.x.s a7, v8
+; RV32-NEXT: vslidedown.vi v8, v8, 1
+; RV32-NEXT: vmv.x.s t0, v8
+; RV32-NEXT: vslidedown.vi v8, v9, 2
+; RV32-NEXT: vmv.x.s t1, v8
+; RV32-NEXT: mul a7, a7, t0
+; RV32-NEXT: mul a5, a6, a5
+; RV32-NEXT: mul a3, a4, a3
+; RV32-NEXT: mul a1, a2, a1
+; RV32-NEXT: vslidedown.vi v8, v10, 2
+; RV32-NEXT: vmv.x.s a2, v8
+; RV32-NEXT: mul a4, a7, a5
+; RV32-NEXT: mul a3, a3, t1
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: mul a1, a4, a3
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: vslidedown.vi v8, v10, 3
+; RV32-NEXT: mul a0, a1, a0
+; RV32-NEXT: vmv.x.s a1, v8
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_mul_nxv6i32_exact_vlen:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v11, v10, 1
+; RV64-NEXT: vmv.x.s a0, v11
+; RV64-NEXT: vmv.x.s a1, v10
+; RV64-NEXT: vslidedown.vi v11, v9, 3
+; RV64-NEXT: vmv.x.s a2, v11
+; RV64-NEXT: vslidedown.vi v11, v9, 1
+; RV64-NEXT: vmv.x.s a3, v11
+; RV64-NEXT: vmv.x.s a4, v9
+; RV64-NEXT: vslidedown.vi v11, v8, 3
+; RV64-NEXT: vmv.x.s a5, v11
+; RV64-NEXT: vslidedown.vi v11, v8, 2
+; RV64-NEXT: vmv.x.s a6, v11
+; RV64-NEXT: vmv.x.s a7, v8
+; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vmv.x.s t0, v8
+; RV64-NEXT: vslidedown.vi v8, v9, 2
+; RV64-NEXT: vmv.x.s t1, v8
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: mul a5, a6, a5
+; RV64-NEXT: mul a3, a4, a3
+; RV64-NEXT: mul a1, a2, a1
+; RV64-NEXT: vslidedown.vi v8, v10, 2
+; RV64-NEXT: vmv.x.s a2, v8
+; RV64-NEXT: mul a4, a7, a5
+; RV64-NEXT: mul a3, a3, t1
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: mul a1, a4, a3
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: vslidedown.vi v8, v10, 3
+; RV64-NEXT: mul a0, a1, a0
+; RV64-NEXT: vmv.x.s a1, v8
+; RV64-NEXT: mulw a0, a0, a1
+; RV64-NEXT: ret
%red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %v)
ret i32 %red
}
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/add.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/add.ll
index 8cdd23ccd3992..43dad2f0e6335 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/add.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/add.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpIAdd %[[Int]] %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpIAdd %[[Int]] %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpIAdd %[[Int]] %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpIAdd %[[Int]] %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpIAdd %[[Int]] %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpIAdd %[[Int]] %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpIAdd %[[Int]] %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpIAdd %[[Int]] %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpIAdd %[[Int]] %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpIAdd %[[Int]] %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpIAdd %[[Int]] %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpIAdd %[[Int]] %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpIAdd %[[Int]] %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpIAdd %[[Int]] %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpIAdd %[[Int]] %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpIAdd %[[Int]] %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/and.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/and.ll
index 80c08b744364d..aea222f28c64b 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/and.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/and.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpBitwiseAnd %[[Int]] %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/mul.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/mul.ll
index f14ad786bff88..14df5580c4d8c 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/mul.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/mul.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpIMul %[[Int]] %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpIMul %[[Int]] %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpIMul %[[Int]] %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpIMul %[[Int]] %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpIMul %[[Int]] %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpIMul %[[Int]] %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpIMul %[[Int]] %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpIMul %[[Int]] %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpIMul %[[Int]] %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpIMul %[[Int]] %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpIMul %[[Int]] %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpIMul %[[Int]] %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpIMul %[[Int]] %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpIMul %[[Int]] %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpIMul %[[Int]] %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpIMul %[[Int]] %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/or.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/or.ll
index 274d78dec9dfd..977a9e1932457 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/or.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/or.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpBitwiseOr %[[Int]] %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smax.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smax.ll
index b1ec8f8a45c34..d0a93e80edd5a 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smax.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smax.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smin.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smin.ll
index 1b10db475fc9e..3d46de9ea3c1c 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smin.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/smin.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umax.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umax.ll
index de0f85437fd28..d02e1f1f4f6ea 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umax.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umax.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umin.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umin.ll
index a20594103470a..b25ae575407c8 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umin.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/umin.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/xor.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/xor.ll
index 3898cb11d38f7..8d6a545c24c9c 100644
--- a/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/xor.ll
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/llvm-vector-reduce/xor.ll
@@ -22,36 +22,36 @@ entry:
; CHECK: %[[ParamVec17Int:.*]] = OpFunctionParameter %[[IntVec17]]
; CHECK: %[[Vec17IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 0
; CHECK: %[[Vec17IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 1
-; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
-; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
-; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
-; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
-; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
-; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
-; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
-; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
-; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
-; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
-; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
-; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
-; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
-; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
-; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR1:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntItem0]] %[[Vec17IntItem1]]
+; CHECK: %[[Vec17IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 2
; CHECK: %[[Vec17IntR2:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR1]] %[[Vec17IntItem2]]
+; CHECK: %[[Vec17IntItem3:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 3
; CHECK: %[[Vec17IntR3:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR2]] %[[Vec17IntItem3]]
+; CHECK: %[[Vec17IntItem4:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 4
; CHECK: %[[Vec17IntR4:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR3]] %[[Vec17IntItem4]]
+; CHECK: %[[Vec17IntItem5:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 5
; CHECK: %[[Vec17IntR5:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR4]] %[[Vec17IntItem5]]
+; CHECK: %[[Vec17IntItem6:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 6
; CHECK: %[[Vec17IntR6:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR5]] %[[Vec17IntItem6]]
+; CHECK: %[[Vec17IntItem7:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 7
; CHECK: %[[Vec17IntR7:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR6]] %[[Vec17IntItem7]]
+; CHECK: %[[Vec17IntItem8:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 8
; CHECK: %[[Vec17IntR8:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR7]] %[[Vec17IntItem8]]
+; CHECK: %[[Vec17IntItem9:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 9
; CHECK: %[[Vec17IntR9:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR8]] %[[Vec17IntItem9]]
+; CHECK: %[[Vec17IntItem10:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 10
; CHECK: %[[Vec17IntR10:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR9]] %[[Vec17IntItem10]]
+; CHECK: %[[Vec17IntItem11:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 11
; CHECK: %[[Vec17IntR11:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR10]] %[[Vec17IntItem11]]
+; CHECK: %[[Vec17IntItem12:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 12
; CHECK: %[[Vec17IntR12:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR11]] %[[Vec17IntItem12]]
+; CHECK: %[[Vec17IntItem13:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 13
; CHECK: %[[Vec17IntR13:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR12]] %[[Vec17IntItem13]]
+; CHECK: %[[Vec17IntItem14:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 14
; CHECK: %[[Vec17IntR14:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR13]] %[[Vec17IntItem14]]
+; CHECK: %[[Vec17IntItem15:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 15
; CHECK: %[[Vec17IntR15:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR14]] %[[Vec17IntItem15]]
+; CHECK: %[[Vec17IntItem16:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec17Int]] 16
; CHECK: %[[Vec17IntR16:.*]] = OpBitwiseXor %[[Int]] %[[Vec17IntR15]] %[[Vec17IntItem16]]
; CHECK: OpReturnValue %[[Vec17IntR16]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
index 39cbd8726400a..292aee52ad1c8 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll
@@ -31,8 +31,8 @@
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpIAdd %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpIAdd %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -48,8 +48,8 @@
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpIAdd %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpIAdd %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -65,8 +65,8 @@
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpIAdd %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpIAdd %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -82,8 +82,8 @@
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpIAdd %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpIAdd %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
index a911cdf094045..4e02dbfc2c115 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll
@@ -31,8 +31,8 @@
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpBitwiseAnd %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpBitwiseAnd %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -48,8 +48,8 @@
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpBitwiseAnd %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpBitwiseAnd %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -65,8 +65,8 @@
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpBitwiseAnd %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpBitwiseAnd %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -82,8 +82,8 @@
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpBitwiseAnd %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpBitwiseAnd %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
index 86e6d42de55d1..8c65e42addeff 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpIMul %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpIMul %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpIMul %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpIMul %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpIMul %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpIMul %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpIMul %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpIMul %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
index 34e5272ecd629..e7e0348c43ca4 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpBitwiseOr %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpBitwiseOr %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpBitwiseOr %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpBitwiseOr %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpBitwiseOr %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpBitwiseOr %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpBitwiseOr %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpBitwiseOr %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
index eafd4e096a728..4a49999a81b78 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] s_max %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] s_max %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] s_max %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] s_max %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] s_max %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] s_max %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
index bbd22d4c6d4c5..8d9c128f36165 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] s_min %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] s_min %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] s_min %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] s_min %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] s_min %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] s_min %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] s_min %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
index 80be288d0b941..a0ddc19d65fc4 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] u_max %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] u_max %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] u_max %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] u_max %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] u_max %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] u_max %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] u_max %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
index 2c4832c877783..2516c0a3ecda1 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] u_min %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] u_min %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] u_min %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] u_min %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] u_min %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] u_min %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] u_min %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
index 2532154cfc15c..d20d754f88ca1 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll
@@ -30,8 +30,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]
; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 0
; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 1
-; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR1:.*]] = OpBitwiseXor %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]
+; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 2
; CHECK: %[[Vec3CharR2:.*]] = OpBitwiseXor %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]
; CHECK: OpReturnValue %[[Vec3CharR2]]
; CHECK: OpFunctionEnd
@@ -47,8 +47,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]
; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 0
; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 1
-; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR1:.*]] = OpBitwiseXor %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]
+; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 2
; CHECK: %[[Vec3ShortR2:.*]] = OpBitwiseXor %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]
; CHECK: OpReturnValue %[[Vec3ShortR2]]
; CHECK: OpFunctionEnd
@@ -64,8 +64,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]
; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 0
; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 1
-; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR1:.*]] = OpBitwiseXor %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]
+; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 2
; CHECK: %[[Vec3IntR2:.*]] = OpBitwiseXor %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]
; CHECK: OpReturnValue %[[Vec3IntR2]]
; CHECK: OpFunctionEnd
@@ -81,8 +81,8 @@ target triple = "spir64-unknown-unknown"
; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]
; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 0
; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 1
-; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR1:.*]] = OpBitwiseXor %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]
+; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 2
; CHECK: %[[Vec3LongR2:.*]] = OpBitwiseXor %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]
; CHECK: OpReturnValue %[[Vec3LongR2]]
; CHECK: OpFunctionEnd
diff --git a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
index a6100dd08d7c6..b30c3ca188d5f 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
@@ -265,9 +265,7 @@ define i1 @test_all_v7i1(<7 x i1> %x) {
; CHECK-NEXT: i32.and $push3=, $pop2, $4
; CHECK-NEXT: i32.and $push4=, $pop3, $5
; CHECK-NEXT: i32.and $push5=, $pop4, $6
-; CHECK-NEXT: i32.const $push6=, 1
-; CHECK-NEXT: i32.and $push7=, $pop5, $pop6
-; CHECK-NEXT: return $pop7
+; CHECK-NEXT: return $pop5
%ret = call i1 @llvm.vector.reduce.and.v7i1(<7 x i1> %x)
ret i1 %ret
}
diff --git a/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll b/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
index 179790c46f33c..eee61b20da9fd 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
@@ -216,25 +216,11 @@ define double @test_v2f64(<2 x double> %a0) {
}
define double @test_v3f64(<3 x double> %a0) {
-; SSE2-LABEL: test_v3f64:
-; SSE2: # %bb.0:
-; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE2-NEXT: shufpd {{.*#+}} xmm2 = xmm2[0],mem[1]
-; SSE2-NEXT: maxpd %xmm2, %xmm0
-; SSE2-NEXT: movapd %xmm0, %xmm1
-; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
-; SSE2-NEXT: maxsd %xmm1, %xmm0
-; SSE2-NEXT: retq
-;
-; SSE41-LABEL: test_v3f64:
-; SSE41: # %bb.0:
-; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1]
-; SSE41-NEXT: maxpd %xmm2, %xmm0
-; SSE41-NEXT: movapd %xmm0, %xmm1
-; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
-; SSE41-NEXT: maxsd %xmm1, %xmm0
-; SSE41-NEXT: retq
+; SSE-LABEL: test_v3f64:
+; SSE: # %bb.0:
+; SSE-NEXT: maxsd %xmm1, %xmm0
+; SSE-NEXT: maxsd %xmm2, %xmm0
+; SSE-NEXT: retq
;
; AVX-LABEL: test_v3f64:
; AVX: # %bb.0:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum.ll b/llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum.ll
index 2ce5aeeaf4d4f..8d8d06d47285f 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/x86-partial-reduction-byte-sum.ll
@@ -602,7 +602,53 @@ define i32 @byte_sum_v24_i32() nounwind {
; SSE2-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; SSE2-NEXT: br i1 [[CMP]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]]
; SSE2: [[MIDDLE_BLOCK]]:
-; SSE2-NEXT: [[EXT:%.*]] = call i32 @llvm.vector.reduce.add.v24i32(<24 x i32> [[ADD]])
+; SSE2-NEXT: [[TMP0:%.*]] = extractelement <24 x i32> [[ADD]], i64 0
+; SSE2-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> [[ADD]], i64 1
+; SSE2-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP0]], [[TMP1]]
+; SSE2-NEXT: [[TMP2:%.*]] = extractelement <24 x i32> [[ADD]], i64 2
+; SSE2-NEXT: [[BIN_RDX1:%.*]] = add i32 [[BIN_RDX]], [[TMP2]]
+; SSE2-NEXT: [[TMP3:%.*]] = extractelement <24 x i32> [[ADD]], i64 3
+; SSE2-NEXT: [[BIN_RDX2:%.*]] = add i32 [[BIN_RDX1]], [[TMP3]]
+; SSE2-NEXT: [[TMP4:%.*]] = extractelement <24 x i32> [[ADD]], i64 4
+; SSE2-NEXT: [[BIN_RDX3:%.*]] = add i32 [[BIN_RDX2]], [[TMP4]]
+; SSE2-NEXT: [[TMP5:%.*]] = extractelement <24 x i32> [[ADD]], i64 5
+; SSE2-NEXT: [[BIN_RDX4:%.*]] = add i32 [[BIN_RDX3]], [[TMP5]]
+; SSE2-NEXT: [[TMP6:%.*]] = extractelement <24 x i32> [[ADD]], i64 6
+; SSE2-NEXT: [[BIN_RDX5:%.*]] = add i32 [[BIN_RDX4]], [[TMP6]]
+; SSE2-NEXT: [[TMP7:%.*]] = extractelement <24 x i32> [[ADD]], i64 7
+; SSE2-NEXT: [[BIN_RDX6:%.*]] = add i32 [[BIN_RDX5]], [[TMP7]]
+; SSE2-NEXT: [[TMP8:%.*]] = extractelement <24 x i32> [[ADD]], i64 8
+; SSE2-NEXT: [[BIN_RDX7:%.*]] = add i32 [[BIN_RDX6]], [[TMP8]]
+; SSE2-NEXT: [[TMP9:%.*]] = extractelement <24 x i32> [[ADD]], i64 9
+; SSE2-NEXT: [[BIN_RDX8:%.*]] = add i32 [[BIN_RDX7]], [[TMP9]]
+; SSE2-NEXT: [[TMP10:%.*]] = extractelement <24 x i32> [[ADD]], i64 10
+; SSE2-NEXT: [[BIN_RDX9:%.*]] = add i32 [[BIN_RDX8]], [[TMP10]]
+; SSE2-NEXT: [[TMP11:%.*]] = extractelement <24 x i32> [[ADD]], i64 11
+; SSE2-NEXT: [[BIN_RDX10:%.*]] = add i32 [[BIN_RDX9]], [[TMP11]]
+; SSE2-NEXT: [[TMP12:%.*]] = extractelement <24 x i32> [[ADD]], i64 12
+; SSE2-NEXT: [[BIN_RDX11:%.*]] = add i32 [[BIN_RDX10]], [[TMP12]]
+; SSE2-NEXT: [[TMP13:%.*]] = extractelement <24 x i32> [[ADD]], i64 13
+; SSE2-NEXT: [[BIN_RDX12:%.*]] = add i32 [[BIN_RDX11]], [[TMP13]]
+; SSE2-NEXT: [[TMP14:%.*]] = extractelement <24 x i32> [[ADD]], i64 14
+; SSE2-NEXT: [[BIN_RDX13:%.*]] = add i32 [[BIN_RDX12]], [[TMP14]]
+; SSE2-NEXT: [[TMP15:%.*]] = extractelement <24 x i32> [[ADD]], i64 15
+; SSE2-NEXT: [[BIN_RDX14:%.*]] = add i32 [[BIN_RDX13]], [[TMP15]]
+; SSE2-NEXT: [[TMP16:%.*]] = extractelement <24 x i32> [[ADD]], i64 16
+; SSE2-NEXT: [[BIN_RDX15:%.*]] = add i32 [[BIN_RDX14]], [[TMP16]]
+; SSE2-NEXT: [[TMP17:%.*]] = extractelement <24 x i32> [[ADD]], i64 17
+; SSE2-NEXT: [[BIN_RDX16:%.*]] = add i32 [[BIN_RDX15]], [[TMP17]]
+; SSE2-NEXT: [[TMP18:%.*]] = extractelement <24 x i32> [[ADD]], i64 18
+; SSE2-NEXT: [[BIN_RDX17:%.*]] = add i32 [[BIN_RDX16]], [[TMP18]]
+; SSE2-NEXT: [[TMP19:%.*]] = extractelement <24 x i32> [[ADD]], i64 19
+; SSE2-NEXT: [[BIN_RDX18:%.*]] = add i32 [[BIN_RDX17]], [[TMP19]]
+; SSE2-NEXT: [[TMP20:%.*]] = extractelement <24 x i32> [[ADD]], i64 20
+; SSE2-NEXT: [[BIN_RDX19:%.*]] = add i32 [[BIN_RDX18]], [[TMP20]]
+; SSE2-NEXT: [[TMP21:%.*]] = extractelement <24 x i32> [[ADD]], i64 21
+; SSE2-NEXT: [[BIN_RDX20:%.*]] = add i32 [[BIN_RDX19]], [[TMP21]]
+; SSE2-NEXT: [[TMP22:%.*]] = extractelement <24 x i32> [[ADD]], i64 22
+; SSE2-NEXT: [[BIN_RDX21:%.*]] = add i32 [[BIN_RDX20]], [[TMP22]]
+; SSE2-NEXT: [[TMP23:%.*]] = extractelement <24 x i32> [[ADD]], i64 23
+; SSE2-NEXT: [[EXT:%.*]] = add i32 [[BIN_RDX21]], [[TMP23]]
; SSE2-NEXT: ret i32 [[EXT]]
;
; SSE42-LABEL: define i32 @byte_sum_v24_i32(
@@ -620,7 +666,53 @@ define i32 @byte_sum_v24_i32() nounwind {
; SSE42-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; SSE42-NEXT: br i1 [[CMP]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]]
; SSE42: [[MIDDLE_BLOCK]]:
-; SSE42-NEXT: [[EXT:%.*]] = call i32 @llvm.vector.reduce.add.v24i32(<24 x i32> [[ADD]])
+; SSE42-NEXT: [[TMP0:%.*]] = extractelement <24 x i32> [[ADD]], i64 0
+; SSE42-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> [[ADD]], i64 1
+; SSE42-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP0]], [[TMP1]]
+; SSE42-NEXT: [[TMP2:%.*]] = extractelement <24 x i32> [[ADD]], i64 2
+; SSE42-NEXT: [[BIN_RDX1:%.*]] = add i32 [[BIN_RDX]], [[TMP2]]
+; SSE42-NEXT: [[TMP3:%.*]] = extractelement <24 x i32> [[ADD]], i64 3
+; SSE42-NEXT: [[BIN_RDX2:%.*]] = add i32 [[BIN_RDX1]], [[TMP3]]
+; SSE42-NEXT: [[TMP4:%.*]] = extractelement <24 x i32> [[ADD]], i64 4
+; SSE42-NEXT: [[BIN_RDX3:%.*]] = add i32 [[BIN_RDX2]], [[TMP4]]
+; SSE42-NEXT: [[TMP5:%.*]] = extractelement <24 x i32> [[ADD]], i64 5
+; SSE42-NEXT: [[BIN_RDX4:%.*]] = add i32 [[BIN_RDX3]], [[TMP5]]
+; SSE42-NEXT: [[TMP6:%.*]] = extractelement <24 x i32> [[ADD]], i64 6
+; SSE42-NEXT: [[BIN_RDX5:%.*]] = add i32 [[BIN_RDX4]], [[TMP6]]
+; SSE42-NEXT: [[TMP7:%.*]] = extractelement <24 x i32> [[ADD]], i64 7
+; SSE42-NEXT: [[BIN_RDX6:%.*]] = add i32 [[BIN_RDX5]], [[TMP7]]
+; SSE42-NEXT: [[TMP8:%.*]] = extractelement <24 x i32> [[ADD]], i64 8
+; SSE42-NEXT: [[BIN_RDX7:%.*]] = add i32 [[BIN_RDX6]], [[TMP8]]
+; SSE42-NEXT: [[TMP9:%.*]] = extractelement <24 x i32> [[ADD]], i64 9
+; SSE42-NEXT: [[BIN_RDX8:%.*]] = add i32 [[BIN_RDX7]], [[TMP9]]
+; SSE42-NEXT: [[TMP10:%.*]] = extractelement <24 x i32> [[ADD]], i64 10
+; SSE42-NEXT: [[BIN_RDX9:%.*]] = add i32 [[BIN_RDX8]], [[TMP10]]
+; SSE42-NEXT: [[TMP11:%.*]] = extractelement <24 x i32> [[ADD]], i64 11
+; SSE42-NEXT: [[BIN_RDX10:%.*]] = add i32 [[BIN_RDX9]], [[TMP11]]
+; SSE42-NEXT: [[TMP12:%.*]] = extractelement <24 x i32> [[ADD]], i64 12
+; SSE42-NEXT: [[BIN_RDX11:%.*]] = add i32 [[BIN_RDX10]], [[TMP12]]
+; SSE42-NEXT: [[TMP13:%.*]] = extractelement <24 x i32> [[ADD]], i64 13
+; SSE42-NEXT: [[BIN_RDX12:%.*]] = add i32 [[BIN_RDX11]], [[TMP13]]
+; SSE42-NEXT: [[TMP14:%.*]] = extractelement <24 x i32> [[ADD]], i64 14
+; SSE42-NEXT: [[BIN_RDX13:%.*]] = add i32 [[BIN_RDX12]], [[TMP14]]
+; SSE42-NEXT: [[TMP15:%.*]] = extractelement <24 x i32> [[ADD]], i64 15
+; SSE42-NEXT: [[BIN_RDX14:%.*]] = add i32 [[BIN_RDX13]], [[TMP15]]
+; SSE42-NEXT: [[TMP16:%.*]] = extractelement <24 x i32> [[ADD]], i64 16
+; SSE42-NEXT: [[BIN_RDX15:%.*]] = add i32 [[BIN_RDX14]], [[TMP16]]
+; SSE42-NEXT: [[TMP17:%.*]] = extractelement <24 x i32> [[ADD]], i64 17
+; SSE42-NEXT: [[BIN_RDX16:%.*]] = add i32 [[BIN_RDX15]], [[TMP17]]
+; SSE42-NEXT: [[TMP18:%.*]] = extractelement <24 x i32> [[ADD]], i64 18
+; SSE42-NEXT: [[BIN_RDX17:%.*]] = add i32 [[BIN_RDX16]], [[TMP18]]
+; SSE42-NEXT: [[TMP19:%.*]] = extractelement <24 x i32> [[ADD]], i64 19
+; SSE42-NEXT: [[BIN_RDX18:%.*]] = add i32 [[BIN_RDX17]], [[TMP19]]
+; SSE42-NEXT: [[TMP20:%.*]] = extractelement <24 x i32> [[ADD]], i64 20
+; SSE42-NEXT: [[BIN_RDX19:%.*]] = add i32 [[BIN_RDX18]], [[TMP20]]
+; SSE42-NEXT: [[TMP21:%.*]] = extractelement <24 x i32> [[ADD]], i64 21
+; SSE42-NEXT: [[BIN_RDX20:%.*]] = add i32 [[BIN_RDX19]], [[TMP21]]
+; SSE42-NEXT: [[TMP22:%.*]] = extractelement <24 x i32> [[ADD]], i64 22
+; SSE42-NEXT: [[BIN_RDX21:%.*]] = add i32 [[BIN_RDX20]], [[TMP22]]
+; SSE42-NEXT: [[TMP23:%.*]] = extractelement <24 x i32> [[ADD]], i64 23
+; SSE42-NEXT: [[EXT:%.*]] = add i32 [[BIN_RDX21]], [[TMP23]]
; SSE42-NEXT: ret i32 [[EXT]]
;
; AVX2-LABEL: define i32 @byte_sum_v24_i32(
@@ -638,7 +730,53 @@ define i32 @byte_sum_v24_i32() nounwind {
; AVX2-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; AVX2-NEXT: br i1 [[CMP]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]]
; AVX2: [[MIDDLE_BLOCK]]:
-; AVX2-NEXT: [[EXT:%.*]] = call i32 @llvm.vector.reduce.add.v24i32(<24 x i32> [[ADD]])
+; AVX2-NEXT: [[TMP0:%.*]] = extractelement <24 x i32> [[ADD]], i64 0
+; AVX2-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> [[ADD]], i64 1
+; AVX2-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP0]], [[TMP1]]
+; AVX2-NEXT: [[TMP2:%.*]] = extractelement <24 x i32> [[ADD]], i64 2
+; AVX2-NEXT: [[BIN_RDX1:%.*]] = add i32 [[BIN_RDX]], [[TMP2]]
+; AVX2-NEXT: [[TMP3:%.*]] = extractelement <24 x i32> [[ADD]], i64 3
+; AVX2-NEXT: [[BIN_RDX2:%.*]] = add i32 [[BIN_RDX1]], [[TMP3]]
+; AVX2-NEXT: [[TMP4:%.*]] = extractelement <24 x i32> [[ADD]], i64 4
+; AVX2-NEXT: [[BIN_RDX3:%.*]] = add i32 [[BIN_RDX2]], [[TMP4]]
+; AVX2-NEXT: [[TMP5:%.*]] = extractelement <24 x i32> [[ADD]], i64 5
+; AVX2-NEXT: [[BIN_RDX4:%.*]] = add i32 [[BIN_RDX3]], [[TMP5]]
+; AVX2-NEXT: [[TMP6:%.*]] = extractelement <24 x i32> [[ADD]], i64 6
+; AVX2-NEXT: [[BIN_RDX5:%.*]] = add i32 [[BIN_RDX4]], [[TMP6]]
+; AVX2-NEXT: [[TMP7:%.*]] = extractelement <24 x i32> [[ADD]], i64 7
+; AVX2-NEXT: [[BIN_RDX6:%.*]] = add i32 [[BIN_RDX5]], [[TMP7]]
+; AVX2-NEXT: [[TMP8:%.*]] = extractelement <24 x i32> [[ADD]], i64 8
+; AVX2-NEXT: [[BIN_RDX7:%.*]] = add i32 [[BIN_RDX6]], [[TMP8]]
+; AVX2-NEXT: [[TMP9:%.*]] = extractelement <24 x i32> [[ADD]], i64 9
+; AVX2-NEXT: [[BIN_RDX8:%.*]] = add i32 [[BIN_RDX7]], [[TMP9]]
+; AVX2-NEXT: [[TMP10:%.*]] = extractelement <24 x i32> [[ADD]], i64 10
+; AVX2-NEXT: [[BIN_RDX9:%.*]] = add i32 [[BIN_RDX8]], [[TMP10]]
+; AVX2-NEXT: [[TMP11:%.*]] = extractelement <24 x i32> [[ADD]], i64 11
+; AVX2-NEXT: [[BIN_RDX10:%.*]] = add i32 [[BIN_RDX9]], [[TMP11]]
+; AVX2-NEXT: [[TMP12:%.*]] = extractelement <24 x i32> [[ADD]], i64 12
+; AVX2-NEXT: [[BIN_RDX11:%.*]] = add i32 [[BIN_RDX10]], [[TMP12]]
+; AVX2-NEXT: [[TMP13:%.*]] = extractelement <24 x i32> [[ADD]], i64 13
+; AVX2-NEXT: [[BIN_RDX12:%.*]] = add i32 [[BIN_RDX11]], [[TMP13]]
+; AVX2-NEXT: [[TMP14:%.*]] = extractelement <24 x i32> [[ADD]], i64 14
+; AVX2-NEXT: [[BIN_RDX13:%.*]] = add i32 [[BIN_RDX12]], [[TMP14]]
+; AVX2-NEXT: [[TMP15:%.*]] = extractelement <24 x i32> [[ADD]], i64 15
+; AVX2-NEXT: [[BIN_RDX14:%.*]] = add i32 [[BIN_RDX13]], [[TMP15]]
+; AVX2-NEXT: [[TMP16:%.*]] = extractelement <24 x i32> [[ADD]], i64 16
+; AVX2-NEXT: [[BIN_RDX15:%.*]] = add i32 [[BIN_RDX14]], [[TMP16]]
+; AVX2-NEXT: [[TMP17:%.*]] = extractelement <24 x i32> [[ADD]], i64 17
+; AVX2-NEXT: [[BIN_RDX16:%.*]] = add i32 [[BIN_RDX15]], [[TMP17]]
+; AVX2-NEXT: [[TMP18:%.*]] = extractelement <24 x i32> [[ADD]], i64 18
+; AVX2-NEXT: [[BIN_RDX17:%.*]] = add i32 [[BIN_RDX16]], [[TMP18]]
+; AVX2-NEXT: [[TMP19:%.*]] = extractelement <24 x i32> [[ADD]], i64 19
+; AVX2-NEXT: [[BIN_RDX18:%.*]] = add i32 [[BIN_RDX17]], [[TMP19]]
+; AVX2-NEXT: [[TMP20:%.*]] = extractelement <24 x i32> [[ADD]], i64 20
+; AVX2-NEXT: [[BIN_RDX19:%.*]] = add i32 [[BIN_RDX18]], [[TMP20]]
+; AVX2-NEXT: [[TMP21:%.*]] = extractelement <24 x i32> [[ADD]], i64 21
+; AVX2-NEXT: [[BIN_RDX20:%.*]] = add i32 [[BIN_RDX19]], [[TMP21]]
+; AVX2-NEXT: [[TMP22:%.*]] = extractelement <24 x i32> [[ADD]], i64 22
+; AVX2-NEXT: [[BIN_RDX21:%.*]] = add i32 [[BIN_RDX20]], [[TMP22]]
+; AVX2-NEXT: [[TMP23:%.*]] = extractelement <24 x i32> [[ADD]], i64 23
+; AVX2-NEXT: [[EXT:%.*]] = add i32 [[BIN_RDX21]], [[TMP23]]
; AVX2-NEXT: ret i32 [[EXT]]
;
; AVX512-LABEL: define i32 @byte_sum_v24_i32(
@@ -656,7 +794,53 @@ define i32 @byte_sum_v24_i32() nounwind {
; AVX512-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; AVX512-NEXT: br i1 [[CMP]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]]
; AVX512: [[MIDDLE_BLOCK]]:
-; AVX512-NEXT: [[EXT:%.*]] = call i32 @llvm.vector.reduce.add.v24i32(<24 x i32> [[ADD]])
+; AVX512-NEXT: [[TMP0:%.*]] = extractelement <24 x i32> [[ADD]], i64 0
+; AVX512-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> [[ADD]], i64 1
+; AVX512-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP0]], [[TMP1]]
+; AVX512-NEXT: [[TMP2:%.*]] = extractelement <24 x i32> [[ADD]], i64 2
+; AVX512-NEXT: [[BIN_RDX1:%.*]] = add i32 [[BIN_RDX]], [[TMP2]]
+; AVX512-NEXT: [[TMP3:%.*]] = extractelement <24 x i32> [[ADD]], i64 3
+; AVX512-NEXT: [[BIN_RDX2:%.*]] = add i32 [[BIN_RDX1]], [[TMP3]]
+; AVX512-NEXT: [[TMP4:%.*]] = extractelement <24 x i32> [[ADD]], i64 4
+; AVX512-NEXT: [[BIN_RDX3:%.*]] = add i32 [[BIN_RDX2]], [[TMP4]]
+; AVX512-NEXT: [[TMP5:%.*]] = extractelement <24 x i32> [[ADD]], i64 5
+; AVX512-NEXT: [[BIN_RDX4:%.*]] = add i32 [[BIN_RDX3]], [[TMP5]]
+; AVX512-NEXT: [[TMP6:%.*]] = extractelement <24 x i32> [[ADD]], i64 6
+; AVX512-NEXT: [[BIN_RDX5:%.*]] = add i32 [[BIN_RDX4]], [[TMP6]]
+; AVX512-NEXT: [[TMP7:%.*]] = extractelement <24 x i32> [[ADD]], i64 7
+; AVX512-NEXT: [[BIN_RDX6:%.*]] = add i32 [[BIN_RDX5]], [[TMP7]]
+; AVX512-NEXT: [[TMP8:%.*]] = extractelement <24 x i32> [[ADD]], i64 8
+; AVX512-NEXT: [[BIN_RDX7:%.*]] = add i32 [[BIN_RDX6]], [[TMP8]]
+; AVX512-NEXT: [[TMP9:%.*]] = extractelement <24 x i32> [[ADD]], i64 9
+; AVX512-NEXT: [[BIN_RDX8:%.*]] = add i32 [[BIN_RDX7]], [[TMP9]]
+; AVX512-NEXT: [[TMP10:%.*]] = extractelement <24 x i32> [[ADD]], i64 10
+; AVX512-NEXT: [[BIN_RDX9:%.*]] = add i32 [[BIN_RDX8]], [[TMP10]]
+; AVX512-NEXT: [[TMP11:%.*]] = extractelement <24 x i32> [[ADD]], i64 11
+; AVX512-NEXT: [[BIN_RDX10:%.*]] = add i32 [[BIN_RDX9]], [[TMP11]]
+; AVX512-NEXT: [[TMP12:%.*]] = extractelement <24 x i32> [[ADD]], i64 12
+; AVX512-NEXT: [[BIN_RDX11:%.*]] = add i32 [[BIN_RDX10]], [[TMP12]]
+; AVX512-NEXT: [[TMP13:%.*]] = extractelement <24 x i32> [[ADD]], i64 13
+; AVX512-NEXT: [[BIN_RDX12:%.*]] = add i32 [[BIN_RDX11]], [[TMP13]]
+; AVX512-NEXT: [[TMP14:%.*]] = extractelement <24 x i32> [[ADD]], i64 14
+; AVX512-NEXT: [[BIN_RDX13:%.*]] = add i32 [[BIN_RDX12]], [[TMP14]]
+; AVX512-NEXT: [[TMP15:%.*]] = extractelement <24 x i32> [[ADD]], i64 15
+; AVX512-NEXT: [[BIN_RDX14:%.*]] = add i32 [[BIN_RDX13]], [[TMP15]]
+; AVX512-NEXT: [[TMP16:%.*]] = extractelement <24 x i32> [[ADD]], i64 16
+; AVX512-NEXT: [[BIN_RDX15:%.*]] = add i32 [[BIN_RDX14]], [[TMP16]]
+; AVX512-NEXT: [[TMP17:%.*]] = extractelement <24 x i32> [[ADD]], i64 17
+; AVX512-NEXT: [[BIN_RDX16:%.*]] = add i32 [[BIN_RDX15]], [[TMP17]]
+; AVX512-NEXT: [[TMP18:%.*]] = extractelement <24 x i32> [[ADD]], i64 18
+; AVX512-NEXT: [[BIN_RDX17:%.*]] = add i32 [[BIN_RDX16]], [[TMP18]]
+; AVX512-NEXT: [[TMP19:%.*]] = extractelement <24 x i32> [[ADD]], i64 19
+; AVX512-NEXT: [[BIN_RDX18:%.*]] = add i32 [[BIN_RDX17]], [[TMP19]]
+; AVX512-NEXT: [[TMP20:%.*]] = extractelement <24 x i32> [[ADD]], i64 20
+; AVX512-NEXT: [[BIN_RDX19:%.*]] = add i32 [[BIN_RDX18]], [[TMP20]]
+; AVX512-NEXT: [[TMP21:%.*]] = extractelement <24 x i32> [[ADD]], i64 21
+; AVX512-NEXT: [[BIN_RDX20:%.*]] = add i32 [[BIN_RDX19]], [[TMP21]]
+; AVX512-NEXT: [[TMP22:%.*]] = extractelement <24 x i32> [[ADD]], i64 22
+; AVX512-NEXT: [[BIN_RDX21:%.*]] = add i32 [[BIN_RDX20]], [[TMP22]]
+; AVX512-NEXT: [[TMP23:%.*]] = extractelement <24 x i32> [[ADD]], i64 23
+; AVX512-NEXT: [[EXT:%.*]] = add i32 [[BIN_RDX21]], [[TMP23]]
; AVX512-NEXT: ret i32 [[EXT]]
;
entry:
>From dd9eb9d66f7660cef3725c91bc5fde81c9bd4613 Mon Sep 17 00:00:00 2001
From: Prajwal <prajwal.kp.1817 at gmail.com>
Date: Sat, 1 Aug 2026 15:00:20 +0530
Subject: [PATCH 2/2] [CodeGen] Pad non-pow2 i1 reductions to a power of 2
instead of scalarizing
---
llvm/lib/CodeGen/ExpandReductions.cpp | 15 +++++--
.../Generic/expand-experimental-reductions.ll | 31 ++++++++++++++
.../WebAssembly/simd-vecreduce-bool.ll | 42 ++++++++++++-------
3 files changed, 71 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp
index bead77c1a07d6..3e12af78b9ca9 100644
--- a/llvm/lib/CodeGen/ExpandReductions.cpp
+++ b/llvm/lib/CodeGen/ExpandReductions.cpp
@@ -23,6 +23,7 @@
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Transforms/Utils/LoopUtils.h"
+#include <numeric>
using namespace llvm;
@@ -127,9 +128,17 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI,
auto *FTy = cast<FixedVectorType>(Vec->getType());
unsigned NumElts = FTy->getNumElements();
- if (FTy->getElementType() == Builder.getInt1Ty() &&
- isPowerOf2_32(NumElts)) {
- Rdx = Builder.CreateBitCast(Vec, Builder.getIntNTy(NumElts));
+ if (FTy->getElementType() == Builder.getInt1Ty()) {
+ unsigned Width = PowerOf2Ceil(NumElts);
+ if (Width != NumElts) {
+ Constant *Identity = ID == Intrinsic::vector_reduce_and
+ ? Constant::getAllOnesValue(FTy)
+ : Constant::getNullValue(FTy);
+ SmallVector<int, 16> Mask(Width);
+ std::iota(Mask.begin(), Mask.end(), 0);
+ Vec = Builder.CreateShuffleVector(Vec, Identity, Mask);
+ }
+ Rdx = Builder.CreateBitCast(Vec, Builder.getIntNTy(Width));
if (ID == Intrinsic::vector_reduce_and) {
Rdx = Builder.CreateICmpEQ(
Rdx, ConstantInt::getAllOnesValue(Rdx->getType()));
diff --git a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
index 130ca02368cff..fa4166edb6145 100644
--- a/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
+++ b/llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
@@ -20,6 +20,9 @@ declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
declare i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8>)
+declare i1 @llvm.vector.reduce.or.v3i1(<3 x i1>)
+declare i1 @llvm.vector.reduce.and.v7i1(<7 x i1>)
+
define i64 @add_i64(<2 x i64> %vec) {
; CHECK-LABEL: @add_i64(
; CHECK-NEXT: entry:
@@ -346,3 +349,31 @@ entry:
%b = call i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8> %a)
ret i8 %b
}
+
+; i1 reductions of a non power of two vector are padded out with the identity
+; element rather than scalarized.
+define i1 @test_or_v3i1(<3 x i1> %a) nounwind {
+; CHECK-LABEL: @test_or_v3i1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <3 x i1> [[A:%.*]], <3 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i4 [[TMP1]], 0
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+entry:
+ %b = call i1 @llvm.vector.reduce.or.v3i1(<3 x i1> %a)
+ ret i1 %b
+}
+
+define i1 @test_and_v7i1(<7 x i1> %a) nounwind {
+; CHECK-LABEL: @test_and_v7i1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <7 x i1> [[A:%.*]], <7 x i1> splat (i1 true), <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[TMP0]] to i8
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
+; CHECK-NEXT: ret i1 [[TMP2]]
+;
+entry:
+ %b = call i1 @llvm.vector.reduce.and.v7i1(<7 x i1> %a)
+ ret i1 %b
+}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
index b30c3ca188d5f..955e2af8dc178 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
@@ -244,13 +244,20 @@ define i1 @test_any_v7i1(<7 x i1> %x) {
; CHECK-LABEL: test_any_v7i1:
; CHECK: .functype test_any_v7i1 (i32, i32, i32, i32, i32, i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.or $push0=, $0, $1
-; CHECK-NEXT: i32.or $push1=, $pop0, $2
-; CHECK-NEXT: i32.or $push2=, $pop1, $3
-; CHECK-NEXT: i32.or $push3=, $pop2, $4
-; CHECK-NEXT: i32.or $push4=, $pop3, $5
-; CHECK-NEXT: i32.or $push5=, $pop4, $6
-; CHECK-NEXT: return $pop5
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i16x8.replace_lane $push1=, $pop0, 0, $0
+; CHECK-NEXT: i16x8.replace_lane $push2=, $pop1, 1, $1
+; CHECK-NEXT: i16x8.replace_lane $push3=, $pop2, 2, $2
+; CHECK-NEXT: i16x8.replace_lane $push4=, $pop3, 3, $3
+; CHECK-NEXT: i16x8.replace_lane $push5=, $pop4, 4, $4
+; CHECK-NEXT: i16x8.replace_lane $push6=, $pop5, 5, $5
+; CHECK-NEXT: i16x8.replace_lane $push7=, $pop6, 6, $6
+; CHECK-NEXT: i32.const $push8=, 15
+; CHECK-NEXT: i16x8.shl $push9=, $pop7, $pop8
+; CHECK-NEXT: i32.const $push12=, 15
+; CHECK-NEXT: i16x8.shr_s $push10=, $pop9, $pop12
+; CHECK-NEXT: v128.any_true $push11=, $pop10
+; CHECK-NEXT: return $pop11
%ret = call i1 @llvm.vector.reduce.or.v7i1(<7 x i1> %x)
ret i1 %ret
}
@@ -259,13 +266,20 @@ define i1 @test_all_v7i1(<7 x i1> %x) {
; CHECK-LABEL: test_all_v7i1:
; CHECK: .functype test_all_v7i1 (i32, i32, i32, i32, i32, i32, i32) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i32.and $push0=, $0, $1
-; CHECK-NEXT: i32.and $push1=, $pop0, $2
-; CHECK-NEXT: i32.and $push2=, $pop1, $3
-; CHECK-NEXT: i32.and $push3=, $pop2, $4
-; CHECK-NEXT: i32.and $push4=, $pop3, $5
-; CHECK-NEXT: i32.and $push5=, $pop4, $6
-; CHECK-NEXT: return $pop5
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 65535
+; CHECK-NEXT: i16x8.replace_lane $push1=, $pop0, 0, $0
+; CHECK-NEXT: i16x8.replace_lane $push2=, $pop1, 1, $1
+; CHECK-NEXT: i16x8.replace_lane $push3=, $pop2, 2, $2
+; CHECK-NEXT: i16x8.replace_lane $push4=, $pop3, 3, $3
+; CHECK-NEXT: i16x8.replace_lane $push5=, $pop4, 4, $4
+; CHECK-NEXT: i16x8.replace_lane $push6=, $pop5, 5, $5
+; CHECK-NEXT: i16x8.replace_lane $push7=, $pop6, 6, $6
+; CHECK-NEXT: i32.const $push8=, 15
+; CHECK-NEXT: i16x8.shl $push9=, $pop7, $pop8
+; CHECK-NEXT: i32.const $push12=, 15
+; CHECK-NEXT: i16x8.shr_s $push10=, $pop9, $pop12
+; CHECK-NEXT: i16x8.all_true $push11=, $pop10
+; CHECK-NEXT: return $pop11
%ret = call i1 @llvm.vector.reduce.and.v7i1(<7 x i1> %x)
ret i1 %ret
}
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