[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Jiaxun Yang via llvm-commits]

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@@ -45,6 +45,77 @@ using namespace llvm;
 #define GET_REGINFO_MC_DESC
 #include "MipsGenRegisterInfo.inc"
 
+#define GET_REGISTER_MATCHER
+#include "MipsGenAsmMatcher.inc"
+
+MCRegister MIPS_MC::matchRegisterName(StringRef Name, const MCRegisterInfo &MRI,
+                                      unsigned RegClassID, unsigned AltIdx) {
+  MCRegister Reg = MatchRegisterAltName(Name, AltIdx);
+  if (!Reg)
+    Reg = MatchRegisterName(Name);
+  if (!Reg)
+    return MCRegister();
+
+  const MCRegisterClass &RC = MRI.getRegClass(RegClassID);
+  // GPR32 and GPR64 share names; select the requested width.
+  if (!RC.contains(Reg)) {
+    if (RegClassID == Mips::GPR32RegClassID &&
+        MRI.getRegClass(Mips::GPR64RegClassID).contains(Reg))
+      Reg = MRI.getSubReg(Reg, Mips::sub_32);
+    else if (RegClassID == Mips::GPR64RegClassID &&
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FlyGoat wrote:

FGR is not using this code path now, maybe yes for future :-) I haven't think about this in detail.

https://github.com/llvm/llvm-project/pull/224284