[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Jiaxun Yang via llvm-commits]

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@@ -26,18 +26,129 @@ cl::opt<bool>
                    cl::init(false));
 
 namespace {
-static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
-
-static const MCPhysReg Mips64IntRegs[8] = {
+static constexpr MCPhysReg O32IntRegs[] = {Mips::A0, Mips::A1, Mips::A2,
+                                           Mips::A3};
+static constexpr MCPhysReg NABIIntRegs[] = {Mips::A0, Mips::A1, Mips::A2,
+                                            Mips::A3, Mips::T0, Mips::T1,
+                                            Mips::T2, Mips::T3};
+static constexpr MCPhysReg Mips64IntRegs[] = {
     Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
     Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
+
+struct GPR {
+  MCPhysReg Reg32;
+  MCPhysReg Reg64;
+};
+
+static constexpr GPR OABITempRegs[] = {
+    {Mips::T0, Mips::T0_64}, {Mips::T1, Mips::T1_64}, {Mips::T2, Mips::T2_64},
+    {Mips::T3, Mips::T3_64}, {Mips::T4, Mips::T4_64}, {Mips::T5, Mips::T5_64},
+    {Mips::T6, Mips::T6_64}, {Mips::T7, Mips::T7_64}, {Mips::T8, Mips::T8_64},
+    {Mips::T9, Mips::T9_64},
+};
+
+static constexpr GPR NABITempRegs[] = {
+    {Mips::T4, Mips::T4_64},
+    {Mips::T5, Mips::T5_64},
+    {Mips::T6, Mips::T6_64},
+    {Mips::T7, Mips::T7_64},
+    {Mips::NoRegister, Mips::NoRegister},
+    {Mips::NoRegister, Mips::NoRegister},
+    {Mips::NoRegister, Mips::NoRegister},
+    {Mips::NoRegister, Mips::NoRegister},
+    {Mips::T8, Mips::T8_64},
+    {Mips::T9, Mips::T9_64},
+};
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FlyGoat wrote:

Mapping between which?

https://github.com/llvm/llvm-project/pull/224284