[llvm] 3c85ce7 - LoongArch: Simplify handling of call pseudo operands when expanding. (#224824)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-09-21T10:00:24+02:00
New Revision: 3c85ce724f447a7c2e439d05817b440cb872edd3

URL: https://github.com/llvm/llvm-project/commit/3c85ce724f447a7c2e439d05817b440cb872edd3
DIFF: https://github.com/llvm/llvm-project/commit/3c85ce724f447a7c2e439d05817b440cb872edd3.diff

LOG: LoongArch: Simplify handling of call pseudo operands when expanding. (#224824)

copyImplicitOperands isn't really intended for the call instruction case
where there are also variadic operands. This avoids duplicating the R1
implicit-def operand when expanding calls. This avoids having mixed dead
and not dead flags on the same register, which will fail a future
verifier check.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
    llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
index 0e18669b56e64..7849fc5a13206 100644
--- a/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
@@ -661,10 +661,6 @@ bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
     MachineBasicBlock::iterator &NextMBBI, bool IsTailCall) {
   MachineFunction *MF = MBB.getParent();
   MachineInstr &MI = *MBBI;
-  DebugLoc DL = MI.getDebugLoc();
-  const MachineOperand &Func = MI.getOperand(0);
-  MachineInstrBuilder CALL;
-  unsigned Opcode;
 
   switch (MF->getTarget().getCodeModel()) {
   default:
@@ -675,15 +671,16 @@ bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
     // bl func
     // TAIL:
     // b func
-    Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
-    CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).add(Func);
-    break;
+    unsigned Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
+    MI.setDesc(TII->get(Opcode));
+    return true;
   }
   case CodeModel::Large: {
     // Emit the 5-insn large address load sequence, either directly or
     // indirectly in case of going through the GOT, then JIRL_TAIL or
     // JIRL_CALL to $addr.
-    Opcode =
+    const MachineOperand &Func = MI.getOperand(0);
+    unsigned Opcode =
         IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
     Register AddrReg =
         IsTailCall
@@ -695,19 +692,16 @@ bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
     unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
     expandLargeAddressLoad(MBB, MBBI, NextMBBI, LAOpcode, MO, Func, AddrReg,
                            false);
-    CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(AddrReg).addImm(0);
-    break;
+
+    // Mutate the pseudo into the JIRL in place, keeping its implicit operands.
+    // Operand 0 becomes the address register; operand 1 is the jump offset.
+    MI.setDesc(TII->get(Opcode));
+    MI.getOperand(0).ChangeToRegister(AddrReg, /*isDef=*/false);
+    MI.insert(std::next(MI.operands_begin()), MachineOperand::CreateImm(0));
+    return true;
   }
   }
-
-  // Transfer implicit operands.
-  CALL.copyImplicitOps(MI);
-
-  // Transfer MI flags.
-  CALL.setMIFlags(MI.getFlags());
-
-  MI.eraseFromParent();
-  return true;
+  llvm_unreachable("Unexpected code model");
 }
 
 void LoongArchPreRAExpandPseudo::annotateTableJump(
@@ -879,8 +873,6 @@ bool LoongArchExpandPseudo::expandFunctionCALL(
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   const MachineOperand &Func = MI.getOperand(0);
-  MachineInstrBuilder CALL;
-  unsigned Opcode;
 
   switch (MF->getTarget().getCodeModel()) {
   default:
@@ -902,7 +894,7 @@ bool LoongArchExpandPseudo::expandFunctionCALL(
     // TAIL:
     //   pcaddu18i $t8, %call36(func)
     //   jirl      $r0, $t8, 0
-    Opcode =
+    unsigned Opcode =
         IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
     Register ScratchReg = IsTailCall ? LoongArch::R20 : LoongArch::R1;
     bool Is64Bit = MF->getSubtarget<LoongArchSubtarget>().is64Bit();
@@ -910,25 +902,20 @@ bool LoongArchExpandPseudo::expandFunctionCALL(
     unsigned MO = Is64Bit ? LoongArchII::MO_CALL36 : LoongArchII::MO_CALL30;
     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(PC), ScratchReg);
 
-    CALL =
-        BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(ScratchReg).addImm(0);
-
     if (Func.isSymbol())
       MIB.addExternalSymbol(Func.getSymbolName(), MO);
     else
       MIB.addDisp(Func, 0, MO);
-    break;
+
+    // Mutate the pseudo into the JIRL in place, keeping its implicit operands.
+    // Operand 0 becomes the address register; operand 1 is the jump offset.
+    MI.setDesc(TII->get(Opcode));
+    MI.getOperand(0).ChangeToRegister(ScratchReg, /*isDef=*/false);
+    MI.insert(std::next(MI.operands_begin()), MachineOperand::CreateImm(0));
+    return true;
   }
   }
-
-  // Transfer implicit operands.
-  CALL.copyImplicitOps(MI);
-
-  // Transfer MI flags.
-  CALL.setMIFlags(MI.getFlags());
-
-  MI.eraseFromParent();
-  return true;
+  llvm_unreachable("Unexpected code model");
 }
 
 bool LoongArchExpandPseudo::expandAddUpperImm(

diff  --git a/llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir b/llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir
index 7511193f1359a..6f816eee230ff 100644
--- a/llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir
+++ b/llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir
@@ -44,7 +44,7 @@ tracksRegLiveness: true
 body:             |
   bb.0.entry:
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $r3, implicit $r3
-    BL target-flags(loongarch-call) @foo, csr_ilp32d_lp64d, implicit-def $r1, implicit-def dead $r1, implicit-def $r3
+    BL target-flags(loongarch-call) @foo, csr_ilp32d_lp64d, implicit-def $r1, implicit-def $r3
     ADJCALLSTACKUP 0, 0, implicit-def dead $r3, implicit $r3
     PseudoRET
 
@@ -55,7 +55,7 @@ tracksRegLiveness: true
 body:             |
   bb.0.entry:
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $r3, implicit $r3
-    BL @foo, csr_ilp32d_lp64d, implicit-def $r1, implicit-def dead $r1, implicit-def $r3
+    BL @foo, csr_ilp32d_lp64d, implicit-def $r1, implicit-def $r3
     ADJCALLSTACKUP 0, 0, implicit-def dead $r3, implicit $r3
     PseudoRET