[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Jiaxun Yang via llvm-commits]

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@@ -45,6 +45,77 @@ using namespace llvm;
 #define GET_REGINFO_MC_DESC
 #include "MipsGenRegisterInfo.inc"
 
+#define GET_REGISTER_MATCHER
+#include "MipsGenAsmMatcher.inc"
+
+MCRegister MIPS_MC::matchRegisterName(StringRef Name, const MCRegisterInfo &MRI,
+                                      unsigned RegClassID, unsigned AltIdx) {
+  MCRegister Reg = MatchRegisterAltName(Name, AltIdx);
+  if (!Reg)
+    Reg = MatchRegisterName(Name);
+  if (!Reg)
+    return MCRegister();
+
+  const MCRegisterClass &RC = MRI.getRegClass(RegClassID);
+  // GPR32 and GPR64 share names; select the requested width.
+  if (!RC.contains(Reg)) {
+    if (RegClassID == Mips::GPR32RegClassID &&
+        MRI.getRegClass(Mips::GPR64RegClassID).contains(Reg))
+      Reg = MRI.getSubReg(Reg, Mips::sub_32);
+    else if (RegClassID == Mips::GPR64RegClassID &&
+             MRI.getRegClass(Mips::GPR32RegClassID).contains(Reg))
+      Reg = MRI.getMatchingSuperReg(Reg, Mips::sub_32, &RC);
+  }
+  return RC.contains(Reg) ? Reg : MCRegister();
+}
+
+int MIPS_MC::getCPURegisterIndex(StringRef Name, const MCRegisterInfo &MRI,
+                                 unsigned AltIdx, bool *IsDeprecated) {
+  if (IsDeprecated)
+    *IsDeprecated = false;
+
+  if (MCRegister Reg =
+          matchRegisterName(Name, MRI, Mips::GPR32RegClassID, AltIdx))
+    return MRI.getEncodingValue(Reg);
+
+  static const struct {
+    StringLiteral Name;
+    MCPhysReg Reg;
+    // NoRegAltName applies to all ABIs.
+    unsigned AltIdx;
+  } Aliases[] = {
+      {"AT", Mips::AT, Mips::NoRegAltName},
+      {"s8", Mips::FP, Mips::NoRegAltName},
+      {"kt0", Mips::K0, Mips::NABIRegAltName},
+      {"kt1", Mips::K1, Mips::NABIRegAltName},
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FlyGoat wrote:

It’s already covered by other register name cases.

PABI test is only possible after nanoMIPS being implemented, it’s a place holder for now.

https://github.com/llvm/llvm-project/pull/224284