[llvm] [SPIRV][NewPM] Do not require RegBankSelect in instruction selection (PR #225023)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/225023

SPIR-V skips RegBankSelect and keeps virtual registers, so the property is never set

Match the legacy pipeline

>From e32d36ded3e226dbedc6da609551ceafd35a58e5 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Mon, 21 Sep 2026 09:08:29 +0200
Subject: [PATCH 1/2] [SPIRV][NewPM] Do not require RegBankSelect in
 instruction selection

SPIR-V skips RegBankSelect and keeps virtual registers, so the property is never set

Match the legacy pipeline, which passes false
---
 llvm/lib/Target/SPIRV/SPIRVCodeGenPassBuilder.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/SPIRV/SPIRVCodeGenPassBuilder.cpp b/llvm/lib/Target/SPIRV/SPIRVCodeGenPassBuilder.cpp
index 34c8060e97de5..4feb8ee2a4699 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCodeGenPassBuilder.cpp
@@ -173,7 +173,9 @@ Error SPIRVCodeGenPassBuilder::addRegBankSelect(PassManagerWrapper &PMW) {
 
 Error SPIRVCodeGenPassBuilder::addGlobalInstructionSelect(
     PassManagerWrapper &PMW) {
-  addMachineFunctionPass(InstructionSelectPass(getOptLevel()), PMW);
+  addMachineFunctionPass(
+      InstructionSelectPass(getOptLevel(), /*RequireRegBankSelection=*/false),
+      PMW);
   return Error::success();
 }
 

>From 07d338ecbf89a8bf2ad95c85383e936d8eab5e41 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Mon, 21 Sep 2026 09:27:19 +0200
Subject: [PATCH 2/2] test

---
 llvm/test/CodeGen/SPIRV/llc-pipeline.ll | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/llvm/test/CodeGen/SPIRV/llc-pipeline.ll b/llvm/test/CodeGen/SPIRV/llc-pipeline.ll
index 7b85311ef5bda..406641b2aa753 100644
--- a/llvm/test/CodeGen/SPIRV/llc-pipeline.ll
+++ b/llvm/test/CodeGen/SPIRV/llc-pipeline.ll
@@ -7,6 +7,10 @@
 ; RUN:   | FileCheck -match-full-lines -strict-whitespace -check-prefix=SPIRV-Opt %s
 ; RUN:llc -O3 -mtriple=spirv-- -disable-verify -debug-pass=Structure < %s 2>&1 \
 ; RUN:   | FileCheck -match-full-lines -strict-whitespace -check-prefix=SPIRV-Opt %s
+; RUN:llc -O0 -mtriple=spirv-- -enable-new-pm -stop-before=spirv-asm-printer < %s \
+; RUN:   | FileCheck -check-prefix=SPIRV-NPM %s
+; RUN:llc -O3 -mtriple=spirv-- -enable-new-pm -stop-before=spirv-asm-printer < %s \
+; RUN:   | FileCheck -check-prefix=SPIRV-NPM %s
 ; REQUIRES:asserts
 
 ; SPIRV-O0:Target Library Information
@@ -226,6 +230,14 @@
 ; SPIRV-Opt-NEXT:      SPIRV Assembly Printer
 ; SPIRV-Opt-NEXT:      Free MachineFunction
 
+; SPIR-V NewPM skips RegBankSelect, so instruction selection must not require it.
+; SPIRV-NPM:legalized:       true
+; SPIRV-NPM-NEXT:regBankSelected: false
+; SPIRV-NPM-NEXT:selected:        true
+; SPIRV-NPM:%[[#VOID:]]:type = OpTypeVoid
+; SPIRV-NPM:%[[#]]:iid = OpFunction %[[#VOID]], 0, %[[#]]
+; SPIRV-NPM:OpReturn
+
 define void @empty() {
   ret void
 }