[llvm] fix `bf16` to `i16` bitcast quieting NaNs (PR #224867)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 20 04:58:04 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-hexagon
Author: Folkert de Vries (folkertdev)
<details>
<summary>Changes</summary>
fixes https://github.com/llvm/llvm-project/issues/97896
Follow the pattern of `f16` to generally put `bfloat16` in `i16` registers (except on Arm which overrides this). Riscv and loongarch also customize the behavior, if i'm reading that right they only use float registers for ABI purposes, and GPRs otherwise.
Simple change, massive diff. Mostly due to amdgpu, but also on e.g. x86 this shrinks the generated assembly a bunch.
---
Patch is 4.37 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/224867.diff
48 Files Affected:
- (modified) llvm/include/llvm/CodeGen/TargetLowering.h (+6)
- (modified) llvm/lib/CodeGen/TargetLoweringBase.cpp (+10-2)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.h (+1)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+8)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+14)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+18073-23612)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll (+1338-1578)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll (+28-64)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll (+2690-3209)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll (+274-303)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll (+178-197)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+6775-7962)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll (+688-799)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+799-916)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll (+33-43)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll (+379-548)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll (+195-236)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll (+195-236)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll (+240-350)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll (+222-260)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll (+222-260)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll (+178-258)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll (+544-808)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll (+424-508)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll (+424-508)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll (+328-496)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll (+133-193)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll (+165-193)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll ()
- (modified) llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll (+8-17)
- (modified) llvm/test/CodeGen/ARM/bf16-instructions.ll (+29)
- (modified) llvm/test/CodeGen/Generic/bfloat.ll (+1-2)
- (modified) llvm/test/CodeGen/Hexagon/autohvx/bf16insert.ll (+15-76)
- (modified) llvm/test/CodeGen/Hexagon/bfloat.ll (+33-97)
- (modified) llvm/test/CodeGen/RISCV/bfloat.ll (+66)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vector-convert-from-arbitrary-fp.ll (+6-11)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll (+154-76)
- (modified) llvm/test/CodeGen/X86/atomic-load-store.ll (+480-1406)
- (modified) llvm/test/CodeGen/X86/atomic-non-integer.ll (+6-42)
- (modified) llvm/test/CodeGen/X86/bf16-fast-isel.ll (+16-22)
- (modified) llvm/test/CodeGen/X86/bfloat-calling-conv-no-sse2.ll (+277-1157)
- (modified) llvm/test/CodeGen/X86/bfloat-calling-conv.ll (+241-649)
- (modified) llvm/test/CodeGen/X86/bfloat-int64-cvt-i686.ll (-26)
- (modified) llvm/test/CodeGen/X86/bfloat.ll (+230-192)
- (modified) llvm/test/CodeGen/X86/ldexp.ll (+2-6)
- (modified) llvm/test/CodeGen/X86/llvm.frexp.ll (+6-13)
- (modified) llvm/test/CodeGen/X86/select-phi-s16-fp.ll (+4-20)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index c08d0e53ec34b..1551f833cbccf 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -571,6 +571,12 @@ class LLVM_ABI TargetLoweringBase {
// values are always passed and returned as f32.
virtual bool useFPRegsForHalfType() const { return false; }
+ // Return true if, for soft-promoted bfloat, the bfloat type should be
+ // passed to and returned from functions as f32. The default behavior is to
+ // pass as i16. If soft-promoted bfloat is not used, this function is
+ // ignored and values are always passed and returned as f32.
+ virtual bool useFPRegsForBFloat16Type() const { return false; }
+
// There are two general methods for expanding a BUILD_VECTOR node:
// 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
// them together.
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index f852f7551ce16..31337cefbb735 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1537,8 +1537,16 @@ void TargetLoweringBase::computeRegisterProperties(
// promote it to f32, because there are no bf16 library calls (except for
// converting from f32 to bf16).
if (!isTypeLegal(MVT::bf16)) {
- NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
- RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
+ // Allow targets to control how we legalize bfloat.
+ bool UseFPRegsForBFloat16Type = useFPRegsForBFloat16Type();
+
+ if (!UseFPRegsForBFloat16Type) {
+ NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::i16];
+ RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::i16];
+ } else {
+ NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
+ RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
+ }
TransformToType[MVT::bf16] = MVT::f32;
ValueTypeActions.setTypeAction(MVT::bf16, TypeSoftPromoteHalf);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 4f95a1cdeb2ef..30838f1772b4a 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -504,6 +504,7 @@ class VectorType;
Value *Accumulator = nullptr) const override;
bool useFPRegsForHalfType() const override { return true; }
+ bool useFPRegsForBFloat16Type() const override { return true; }
protected:
std::pair<const TargetRegisterClass *, uint8_t>
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 07f6a438bbb1b..bd871c52c7569 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -11837,6 +11837,10 @@ MVT LoongArchTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
if (VT == MVT::f16 && Subtarget.hasBasicF())
return MVT::f32;
+ // Use f32 to pass bf16.
+ if (VT == MVT::bf16 && Subtarget.hasBasicF())
+ return MVT::f32;
+
return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
}
@@ -11846,6 +11850,10 @@ unsigned LoongArchTargetLowering::getNumRegistersForCallingConv(
if (VT == MVT::f16 && Subtarget.hasBasicF())
return 1;
+ // Use f32 to pass bf16.
+ if (VT == MVT::bf16 && Subtarget.hasBasicF())
+ return 1;
+
return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2c05e3000c5eb..0ad546140554f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2961,6 +2961,13 @@ MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
!Subtarget.hasStdExtZfhminOrZhinxmin())
return MVT::f32;
+ // Use f32 to pass bf16 if it is legal and Zfbfmin/XAndesBFHCvt is not
+ // enabled. We might still end up using a GPR but that will be decided based
+ // on ABI.
+ if (VT == MVT::bf16 && Subtarget.hasStdExtFOrZfinx() &&
+ !Subtarget.hasStdExtZfbfmin() && !Subtarget.hasVendorXAndesBFHCvt())
+ return MVT::f32;
+
return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
}
@@ -2984,6 +2991,13 @@ unsigned RISCVTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context
!Subtarget.hasStdExtZfhminOrZhinxmin())
return 1;
+ // Use f32 to pass bf16 if it is legal and Zfbfmin/XAndesBFHCvt is not
+ // enabled. We might still end up using a GPR but that will be decided based
+ // on ABI.
+ if (VT == MVT::bf16 && Subtarget.hasStdExtFOrZfinx() &&
+ !Subtarget.hasStdExtZfbfmin() && !Subtarget.hasVendorXAndesBFHCvt())
+ return 1;
+
return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 47468f3c7c4cf..428959a141f38 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -21956,596 +21956,223 @@ define <64 x bfloat> @bitcast_v32i32_to_v64bf16(<32 x i32> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; kill: killed $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; kill: killed $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB16_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v62
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
-; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19
-; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v32, v31, v30, 16
+; SI-NEXT: v_alignbit_b32 v33, v29, v28, 16
+; SI-NEXT: v_alignbit_b32 v34, v27, v26, 16
+; SI-NEXT: v_alignbit_b32 v35, v25, v24, 16
+; SI-NEXT: v_alignbit_b32 v36, v23, v22, 16
+; SI-NEXT: v_alignbit_b32 v37, v21, v20, 16
+; SI-NEXT: v_alignbit_b32 v38, v19, v18, 16
+; SI-NEXT: v_alignbit_b32 v39, v17, v16, 16
+; SI-NEXT: v_alignbit_b32 v48, v15, v14, 16
+; SI-NEXT: v_alignbit_b32 v49, v13, v12, 16
+; SI-NEXT: v_alignbit_b32 v50, v11, v10, 16
+; SI-NEXT: v_alignbit_b32 v53, v9, v8, 16
+; SI-NEXT: v_alignbit_b32 v55, v7, v6, 16
+; SI-NEXT: v_alignbit_b32 v42, v5, v4, 16
+; SI-NEXT: v_alignbit_b32 v44, v3, v2, 16
+; SI-NEXT: v_alignbit_b32 v47, v1, v0, 16
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v29
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v27
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v15
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v13
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v11
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v9
+; SI-NEXT: s_waitcnt expcnt(3)
+; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v7
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v5
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v3
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v62
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v14
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v13
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v13
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v12
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v12
-; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v11
-; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v10
-; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v9
-; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v8
-; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v7
-; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v7
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v6
-; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v5
-; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v5
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v4
-; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v3
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v2
-; SI-NEXT: v_and_b32_e32 v59, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v1
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr25
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v1
; SI-NEXT: .LBB16_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB16_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v62
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v31
-; SI-NEXT: v_lshlre...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/224867
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