[llvm] [RISCV] Make Za64rs imply Za128rs (PR #206638)

[Ying Wang via llvm-commits]

https://github.com/yingwang-bj updated https://github.com/llvm/llvm-project/pull/206638

>From 3212ff252dfb4fb42710092a6f95bc3c4c708002 Mon Sep 17 00:00:00 2001
From: Ying Wang <wy446777 at alibaba-inc.com>
Date: Fri, 26 Jun 2026 19:59:32 +0800
Subject: [PATCH] [RISCV] Make Za64rs imply Za128rs

Per the RISC-V ISA specification, the Za64rs extension implies the
Za128rs extension. This change adds Za128rs to the implied extensions
list of Za64rs in RISCVFeatures.td, so that enabling Za64rs
automatically enables Za128rs.

Specification reference:
https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-dc8bf2a-2026-06-26/src/unpriv/zars.adoc

The test expectation in attribute-arch.s is updated to reflect that
za64rs now implies za128rs in the arch attribute string.
---
 llvm/lib/Target/RISCV/RISCVFeatures.td | 7 ++++---
 llvm/test/MC/RISCV/attribute-arch.s    | 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index ca68611339ee1..ae1847ce41517 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -263,12 +263,13 @@ def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
                         "'Ztso' (Memory Model - Total Store Order)">;
 def NoStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 
-def FeatureStdExtZa64rs
-    : RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes">;
-
 def FeatureStdExtZa128rs
     : RISCVExtension<1, 0, "Reservation Set Size of at Most 128 Bytes">;
 
+def FeatureStdExtZa64rs
+    : RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes",
+                     [FeatureStdExtZa128rs]>;
+
 def FeatureStdExtZabha
     : RISCVExtension<1, 0, "Byte and Halfword Atomic Memory Operations",
                      [FeatureStdExtZaamo]>,
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 6d66a190b8e23..5a1d258656ad4 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -286,7 +286,7 @@
 # CHECK: attribute      5, "rv32i2p1_za128rs1p0"
 
 .attribute arch, "rv32iza64rs1p0"
-# CHECK: attribute      5, "rv32i2p1_za64rs1p0"
+# CHECK: attribute      5, "rv32i2p1_za128rs1p0_za64rs1p0"
 
 .attribute arch, "rv32izama16b"
 # CHECK: attribute      5, "rv32i2p1_zama16b1p0"