[llvm] [VPlan] Remove dead per-lane loop from VPScalarIVStepsRecipe::execute. (PR #224399)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 18 12:20:48 PDT 2026
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/224399
>From dc05051c47c3eed4f5aee711ed42b2ddf97142b3 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Thu, 17 Sep 2026 17:53:34 +0100
Subject: [PATCH] [VPlan] Remove dead per-lane loop from
VPScalarIVStepsRecipe::execute.
replicateByVF already materializes every lane of a VPScalarIVStepsRecipe
as its own single-scalar clone, folding the lane offset into the clone's start
index (addLaneToStartIndex).
During execute, each VPScalarIVStepsRecipe has exactly its single lane
used.
Replace it with the lane-0 body and an assert. Note that this removes a
few redundant add start, 0.
---
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 33 +++++--------------
.../AArch64/force-target-instruction-cost.ll | 3 +-
.../AArch64/interleave-with-gaps.ll | 18 ++++------
.../AArch64/sve-gather-scatter.ll | 3 +-
.../AArch64/sve-interleaved-access-low-vf.ll | 3 +-
.../AArch64/sve-tail-folding-option.ll | 27 +++++----------
.../LoopVectorize/AArch64/sve-widen-phi.ll | 3 +-
...form-narrow-interleave-vscale-x-UF-step.ll | 3 +-
.../LoopVectorize/RISCV/strided-accesses.ll | 15 +++------
9 files changed, 34 insertions(+), 74 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 5997b6e0fef76..452589bafd534 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -3268,30 +3268,15 @@ void VPScalarIVStepsRecipe::execute(VPTransformState &State) {
MulOp = Instruction::FMul;
}
- // Determine the number of scalars we need to generate.
- bool FirstLaneOnly = vputils::onlyFirstLaneUsed(this);
- // Compute the scalar steps and save the results in State.
-
- unsigned EndLane = FirstLaneOnly ? 1 : State.VF.getKnownMinValue();
- Value *StartIdx0 = getStartIndex() ? State.get(getStartIndex(), true)
- : Constant::getNullValue(BaseIVTy);
-
- for (unsigned Lane = 0; Lane < EndLane; ++Lane) {
- // It is okay if the induction variable type cannot hold the lane number,
- // we expect truncation in this case.
- Constant *LaneValue =
- BaseIVTy->isIntegerTy()
- ? ConstantInt::get(BaseIVTy, Lane, /*IsSigned=*/false,
- /*ImplicitTrunc=*/true)
- : ConstantFP::get(BaseIVTy, Lane);
- Value *StartIdx = Builder.CreateBinOp(AddOp, StartIdx0, LaneValue);
- assert((State.VF.isScalable() || isa<Constant>(StartIdx)) &&
- "Expected StartIdx to be folded to a constant when VF is not "
- "scalable");
- auto *Mul = Builder.CreateBinOp(MulOp, StartIdx, Step);
- auto *Add = Builder.CreateBinOp(AddOp, BaseIV, Mul);
- State.set(this, Add, VPLane(Lane));
- }
+ // Lanes other than the first have been materialized as separate
+ // single-scalar recipes by replicateByVF, each with its own start index.
+ assert((vputils::onlyFirstLaneUsed(this) || State.VF.isScalar()) &&
+ "must have been replicated by VF");
+ Value *StartIdx = getStartIndex() ? State.get(getStartIndex(), true)
+ : Constant::getNullValue(BaseIVTy);
+ auto *Mul = Builder.CreateBinOp(MulOp, StartIdx, Step);
+ auto *Add = Builder.CreateBinOp(AddOp, BaseIV, Mul);
+ State.set(this, Add, VPLane(0));
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
index 081e2a18df04f..e953b3f7defe0 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
@@ -450,8 +450,7 @@ define void @interleave_group(ptr %dst) #1 {
; COST1-NEXT: br label %[[VECTOR_BODY:.*]]
; COST1: [[VECTOR_BODY]]:
; COST1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; COST1-NEXT: [[TMP28:%.*]] = add i64 [[TMP26]], 0
-; COST1-NEXT: [[TMP5:%.*]] = mul i64 [[TMP28]], 1
+; COST1-NEXT: [[TMP5:%.*]] = mul i64 [[TMP26]], 1
; COST1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], [[TMP5]]
; COST1-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], 3
; COST1-NEXT: [[TMP2:%.*]] = mul i64 [[TMP0]], 3
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
index 9546ff41240fe..e774cd90ead36 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
@@ -390,16 +390,13 @@ define i32 @load_factor_4_with_gap(i64 %n, ptr noalias %a) {
; CHECK-NOTF-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NOTF-NEXT: [[VEC_PHI3:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP41:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NOTF-NEXT: [[VEC_PHI4:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP42:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NOTF-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 0
-; CHECK-NOTF-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 1
+; CHECK-NOTF-NEXT: [[TMP5:%.*]] = mul i64 [[TMP2]], 1
; CHECK-NOTF-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], [[TMP5]]
; CHECK-NOTF-NEXT: [[TMP22:%.*]] = shl i64 [[TMP2]], 1
-; CHECK-NOTF-NEXT: [[TMP23:%.*]] = add i64 [[TMP22]], 0
-; CHECK-NOTF-NEXT: [[TMP24:%.*]] = mul i64 [[TMP23]], 1
+; CHECK-NOTF-NEXT: [[TMP24:%.*]] = mul i64 [[TMP22]], 1
; CHECK-NOTF-NEXT: [[TMP31:%.*]] = add i64 [[INDEX]], [[TMP24]]
; CHECK-NOTF-NEXT: [[TMP32:%.*]] = mul i64 [[TMP2]], 3
-; CHECK-NOTF-NEXT: [[TMP35:%.*]] = add i64 [[TMP32]], 0
-; CHECK-NOTF-NEXT: [[TMP36:%.*]] = mul i64 [[TMP35]], 1
+; CHECK-NOTF-NEXT: [[TMP36:%.*]] = mul i64 [[TMP32]], 1
; CHECK-NOTF-NEXT: [[TMP39:%.*]] = add i64 [[INDEX]], [[TMP36]]
; CHECK-NOTF-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i32], ptr [[A]], i64 [[INDEX]], i32 0
; CHECK-NOTF-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i32], ptr [[A]], i64 [[TMP6]], i32 0
@@ -700,16 +697,13 @@ define i32 @load_factor_4_with_tail_gap(i64 %n, ptr noalias %a) {
; CHECK-NOTF-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NOTF-NEXT: [[VEC_PHI3:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP43:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NOTF-NEXT: [[VEC_PHI4:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP44:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NOTF-NEXT: [[TMP6:%.*]] = add i64 [[TMP2]], 0
-; CHECK-NOTF-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 1
+; CHECK-NOTF-NEXT: [[TMP7:%.*]] = mul i64 [[TMP2]], 1
; CHECK-NOTF-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], [[TMP7]]
; CHECK-NOTF-NEXT: [[TMP24:%.*]] = shl i64 [[TMP2]], 1
-; CHECK-NOTF-NEXT: [[TMP25:%.*]] = add i64 [[TMP24]], 0
-; CHECK-NOTF-NEXT: [[TMP26:%.*]] = mul i64 [[TMP25]], 1
+; CHECK-NOTF-NEXT: [[TMP26:%.*]] = mul i64 [[TMP24]], 1
; CHECK-NOTF-NEXT: [[TMP33:%.*]] = add i64 [[INDEX]], [[TMP26]]
; CHECK-NOTF-NEXT: [[TMP34:%.*]] = mul i64 [[TMP2]], 3
-; CHECK-NOTF-NEXT: [[TMP37:%.*]] = add i64 [[TMP34]], 0
-; CHECK-NOTF-NEXT: [[TMP38:%.*]] = mul i64 [[TMP37]], 1
+; CHECK-NOTF-NEXT: [[TMP38:%.*]] = mul i64 [[TMP34]], 1
; CHECK-NOTF-NEXT: [[TMP41:%.*]] = add i64 [[INDEX]], [[TMP38]]
; CHECK-NOTF-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i32], ptr [[A]], i64 [[INDEX]], i32 0
; CHECK-NOTF-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i32], ptr [[A]], i64 [[TMP8]], i32 0
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
index 341397a83c19b..aeb675b5284c3 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
@@ -217,8 +217,7 @@ define void @gather_nxv4i32_ind64_stride2(ptr noalias nocapture %a, ptr noalias
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP4]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP9]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], [[TMP3]]
; CHECK-NEXT: [[TMP13:%.*]] = shl i64 [[INDEX]], 1
; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[TMP8]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll
index 5e3711d0dee57..58958b27f4d8c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-access-low-vf.ll
@@ -27,8 +27,7 @@ define void @uitofp_nxv8i16_to_nxv8f64_deinterleave(ptr noalias readonly %src, p
; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi double [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP30:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi double [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP32:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi double [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP34:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP2]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = shl nuw i64 [[INDEX]], 2
; CHECK-NEXT: [[TMP8:%.*]] = shl nuw i64 [[TMP6]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
index 64c3f9ae42265..c0285792cd066 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
@@ -899,8 +899,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-NOTF-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-NOTF: [[VECTOR_BODY]]:
; CHECK-NOTF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NOTF-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-NOTF-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-NOTF-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-NOTF-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-NOTF-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-NOTF-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -944,8 +943,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-TF-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-TF: [[VECTOR_BODY]]:
; CHECK-TF-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-TF-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-TF-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-TF-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-TF-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-TF-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-TF-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -989,8 +987,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-TF-SIMPLE-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-TF-SIMPLE: [[VECTOR_BODY]]:
; CHECK-TF-SIMPLE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-TF-SIMPLE-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-TF-SIMPLE-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-TF-SIMPLE-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-TF-SIMPLE-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-TF-SIMPLE-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-TF-SIMPLE-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -1037,8 +1034,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-TF-DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-TF-DEFAULT: [[VECTOR_BODY]]:
; CHECK-TF-DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-TF-DEFAULT-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-TF-DEFAULT-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-TF-DEFAULT-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-TF-DEFAULT-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-TF-DEFAULT-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-TF-DEFAULT-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -1109,8 +1105,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-TF-NORED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-TF-NORED: [[VECTOR_BODY]]:
; CHECK-TF-NORED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-TF-NORED-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-TF-NORED-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-TF-NORED-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-TF-NORED-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-TF-NORED-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-TF-NORED-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -1154,8 +1149,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-TF-NOREC-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-TF-NOREC: [[VECTOR_BODY]]:
; CHECK-TF-NOREC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-TF-NOREC-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-TF-NOREC-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-TF-NOREC-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-TF-NOREC-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-TF-NOREC-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-TF-NOREC-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -1199,8 +1193,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-TF-NOREV-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-TF-NOREV: [[VECTOR_BODY]]:
; CHECK-TF-NOREV-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-TF-NOREV-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-TF-NOREV-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-TF-NOREV-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-TF-NOREV-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-TF-NOREV-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-TF-NOREV-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -1244,8 +1237,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-TF-ONLYRED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-TF-ONLYRED: [[VECTOR_BODY]]:
; CHECK-TF-ONLYRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-TF-ONLYRED-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-TF-ONLYRED-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-TF-ONLYRED-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-TF-ONLYRED-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-TF-ONLYRED-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-TF-ONLYRED-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
@@ -1292,8 +1284,7 @@ define void @interleave(ptr noalias %dst, ptr noalias %src, i64 %n) #0 {
; CHECK-NEOVERSE-V1-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-NEOVERSE-V1: [[VECTOR_BODY]]:
; CHECK-NEOVERSE-V1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEOVERSE-V1-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], 0
-; CHECK-NEOVERSE-V1-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 1
+; CHECK-NEOVERSE-V1-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], 1
; CHECK-NEOVERSE-V1-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], [[TMP4]]
; CHECK-NEOVERSE-V1-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-NEOVERSE-V1-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
index 00d7c318a35a5..6240954578dee 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
@@ -31,8 +31,7 @@ define void @widen_ptr_phi_unrolled(ptr noalias nocapture %a, ptr noalias nocapt
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 3
-; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP3]], 0
-; CHECK-NEXT: [[TMP21:%.*]] = mul i64 [[TMP16]], 8
+; CHECK-NEXT: [[TMP21:%.*]] = mul i64 [[TMP3]], 8
; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[OFFSET_IDX]], [[TMP21]]
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[C]], i64 [[OFFSET_IDX]]
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[C]], i64 [[TMP27]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-vscale-x-UF-step.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-vscale-x-UF-step.ll
index d61e4d2799e27..d07c11d0f90ae 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-vscale-x-UF-step.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-vscale-x-UF-step.ll
@@ -26,8 +26,7 @@ define void @test(ptr noalias %A, i64 %v, i64 %n) {
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[TMP17:%.*]] = phi i64 [ 0, %[[VECTOR_PH2]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP0]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 1
+; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP0]], 1
; CHECK-NEXT: [[INDEX9:%.*]] = add i64 [[TMP17]], [[TMP6]]
; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds { i64, i64 }, ptr [[A]], i64 [[TMP17]], i32 0
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds { i64, i64 }, ptr [[A]], i64 [[INDEX9]], i32 0
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
index 8bdb99909925a..b7c6b498c684f 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
@@ -239,8 +239,7 @@ define void @single_constant_stride_ptr_iv(ptr %p) vscale_range(2, 1024) {
; CHECK-UF2: [[VECTOR_BODY]]:
; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-UF2-NEXT: [[TMP9:%.*]] = shl i64 [[INDEX]], 3
-; CHECK-UF2-NEXT: [[TMP10:%.*]] = add i64 [[TMP3]], 0
-; CHECK-UF2-NEXT: [[TMP11:%.*]] = mul i64 [[TMP10]], 8
+; CHECK-UF2-NEXT: [[TMP11:%.*]] = mul i64 [[TMP3]], 8
; CHECK-UF2-NEXT: [[TMP22:%.*]] = add i64 [[TMP9]], [[TMP11]]
; CHECK-UF2-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP9]]
; CHECK-UF2-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP22]]
@@ -1401,8 +1400,7 @@ define void @interleaved_load_instead_of_strided(ptr %a) vscale_range(2, 1024) {
; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-UF2: [[VECTOR_BODY]]:
; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-UF2-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], 0
-; CHECK-UF2-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 1
+; CHECK-UF2-NEXT: [[TMP5:%.*]] = mul i64 [[TMP3]], 1
; CHECK-UF2-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], [[TMP5]]
; CHECK-UF2-NEXT: [[TMP7:%.*]] = getelementptr [4 x i32], ptr [[A]], i64 [[INDEX]]
; CHECK-UF2-NEXT: [[TMP9:%.*]] = getelementptr [4 x i32], ptr [[A]], i64 [[TMP6]]
@@ -1678,8 +1676,7 @@ define void @lshr_exact_stride(ptr noalias %in, ptr noalias %out) vscale_range(2
; CHECK-UF2: [[VECTOR_BODY]]:
; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-UF2-NEXT: [[TMP10:%.*]] = shl nuw i64 [[INDEX]], 2
-; CHECK-UF2-NEXT: [[TMP11:%.*]] = add i64 [[TMP2]], 0
-; CHECK-UF2-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 4
+; CHECK-UF2-NEXT: [[TMP12:%.*]] = mul i64 [[TMP2]], 4
; CHECK-UF2-NEXT: [[TMP13:%.*]] = add i64 [[TMP10]], [[TMP12]]
; CHECK-UF2-NEXT: [[TMP14:%.*]] = lshr exact i64 [[TMP10]], 1
; CHECK-UF2-NEXT: [[TMP15:%.*]] = lshr exact i64 [[TMP13]], 1
@@ -1779,8 +1776,7 @@ define void @or_disjoint_stride(ptr noalias %in, ptr noalias %out) vscale_range(
; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-UF2: [[VECTOR_BODY]]:
; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-UF2-NEXT: [[TMP6:%.*]] = add i64 [[TMP2]], 0
-; CHECK-UF2-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 1
+; CHECK-UF2-NEXT: [[TMP7:%.*]] = mul i64 [[TMP2]], 1
; CHECK-UF2-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], [[TMP7]]
; CHECK-UF2-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[INDEX]], 1
; CHECK-UF2-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[TMP8]], 1
@@ -1885,8 +1881,7 @@ define void @lshr_stride_no_exact(ptr noalias %in, ptr noalias %out) vscale_rang
; CHECK-UF2: [[VECTOR_BODY]]:
; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-UF2-NEXT: [[TMP10:%.*]] = shl nuw i64 [[INDEX]], 2
-; CHECK-UF2-NEXT: [[TMP11:%.*]] = add i64 [[TMP2]], 0
-; CHECK-UF2-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 4
+; CHECK-UF2-NEXT: [[TMP12:%.*]] = mul i64 [[TMP2]], 4
; CHECK-UF2-NEXT: [[TMP13:%.*]] = add i64 [[TMP10]], [[TMP12]]
; CHECK-UF2-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP10]], 1
; CHECK-UF2-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 1
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