[llvm] [TableGen] Share identical super-register class masks (PR #224633)

[Nick Desaulniers via llvm-commits]

================
@@ -1291,18 +1327,31 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
     OS << "    // " << StartIndices[Idx].SubClassMaskIdx << " " << RC.getName()
        << "\n    ";
     printBitVectorAsHex(OS, RC.getSubClasses(), 32);
+    OS << "\n";
+  }
 
-    // Emit super-reg class masks for any relevant SubRegIndices that can
-    // project into RC.
-    for (auto &Idx : SubRegIndices) {
-      MaskBV.reset();
-      RC.getSuperRegClasses(&Idx, MaskBV);
-      if (MaskBV.none())
-        continue;
-      OS << "\n    ";
-      printBitVectorAsHex(OS, MaskBV, 32);
-      OS << "// " << Idx.getName();
-    }
+  // Emit the pool of super-reg class masks, shared by all the classes that
+  // project into the same set of classes under some sub-register index.
+  for (const auto &[Idx, Mask] : enumerate(MaskPool)) {
+    OS << "    /* " << MaskPoolStarts[Idx] << " */ ";
+    for (uint32_t Word : Mask)
+      OS << format("0x%08x, ", Word);
+    OS << "\n";
+  }
----------------
nickdesaulniers wrote:

With the above suggested change to llvm/utils/TableGen/RegisterInfoEmitter.cpp,


```suggestion
  for (const auto &[Idx, Mask] : enumerate(MaskPool)) {
    OS << "    /* " << MaskPoolStarts[Idx] << " */ ";
    printBitVectorAsHex(OS, Mask, 32);
    OS << "\n";
  }
```

https://github.com/llvm/llvm-project/pull/224633