[llvm] [RISCV] Add OPERAND_UIMM4_PLUS1 to RISCVInstrInfo::verifyInstruction (PR #224423)

[via llvm-commits]

https://github.com/sihuan created https://github.com/llvm/llvm-project/pull/224423

It is used by psati.h and psati.dh.

>From 3ba62d4a6ff409b9a7faf6b0382b2197678570da Mon Sep 17 00:00:00 2001
From: SiHuaN <liyongtai at iscas.ac.cn>
Date: Thu, 17 Sep 2026 20:40:14 +0000
Subject: [PATCH] [RISCV] Add OPERAND_UIMM4_PLUS1 to
 RISCVInstrInfo::verifyInstruction

It is used by psati.h and psati.dh.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6d83480fa6c69..b057c6066516f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3046,6 +3046,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         CASE_OPERAND_UIMM_LSB_ZEROS(8, 000)
         CASE_OPERAND_UIMM_LSB_ZEROS(9, 000)
         // clang-format on
+        case RISCVOp::OPERAND_UIMM4_PLUS1:
+          Ok = Imm >= 1 && Imm <= 16;
+          break;
         case RISCVOp::OPERAND_UIMM5_NONZERO:
           Ok = isUInt<5>(Imm) && (Imm != 0);
           break;