[llvm] [Mips][nanoMIPS] Add initial nanoMIPS target support (PR #223032)

[Jiaxun Yang via llvm-commits]

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@@ -351,6 +548,154 @@ def GPRMM16MovePPairSecond : RegisterClass<"Mips", [i32], 32, (add
   // Callee save
   S5, S6)>;
 
+class GPRNM32Class<list<ValueType> regTypes> :
+  RegisterClass<"Mips", regTypes, 32, (add
+  // Reserved
+  ZERO_NM, AT_NM,
+  // Not preserved across procedure calls
+  T4_NM, T5_NM,
+  // Return Values and Arguments
+  A0_NM, A1_NM, A2_NM, A3_NM, A4_NM, A5_NM, A6_NM, A7_NM,
+  // Not preserved across procedure calls
+  T0_NM, T1_NM, T2_NM, T3_NM,
+  // Callee save
+  S0_NM, S1_NM, S2_NM, S3_NM, S4_NM, S5_NM, S6_NM, S7_NM,
+  // Not preserved across procedure calls
+  T8_NM, T9_NM,
+  // Reserved
+  K0_NM, K1_NM, GP_NM, SP_NM, FP_NM, RA_NM)>;
+
+def GPRNM32 : GPRNM32Class<[i32]>;
+
+class COP0SelRegClassNM<list<ValueType> regTypes> :
+  RegisterClass<"Mips", regTypes, 32, (add
+  COP0Sel_INDEX, COP0Sel_MVPCONTROL, COP0Sel_MVPCONF0, COP0Sel_MVPCONF1,
+  COP0Sel_VPCONTROL, COP0Sel_RANDOM, COP0Sel_VPECONTROL, COP0Sel_VPECONF0,
+  COP0Sel_VPECONF1, COP0Sel_YQMASK, COP0Sel_VPESCHEDULE, COP0Sel_VPESCHEFBACK,
+  COP0Sel_VPEOPT, COP0Sel_ENTRYLO0, COP0Sel_TCSTATUS, COP0Sel_TCBIND,
+  COP0Sel_TCRESTART, COP0Sel_TCHALT, COP0Sel_TCCONTEXT, COP0Sel_TCSCHEDULE,
+  COP0Sel_TCSCHEFBACK, COP0Sel_ENTRYLO1, COP0Sel_GLOBALNUMBER, COP0Sel_TCOPT,
+  COP0Sel_CONTEXT, COP0Sel_CONTEXTCONFIG, COP0Sel_USERLOCAL,
+  COP0Sel_XCONTEXTCONFIG, COP0Sel_DEBUGCONTEXTID, COP0Sel_MEMORYMAPID,
+  COP0Sel_PAGEMASK, COP0Sel_PAGEGRAIN, COP0Sel_SEGCTL0, COP0Sel_SEGCTL1,
+  COP0Sel_SEGCTL2, COP0Sel_PWBASE, COP0Sel_PWFIELD, COP0Sel_PWSIZE,
+  COP0Sel_WIRED, COP0Sel_SRSCONF0, COP0Sel_SRSCONF1, COP0Sel_SRSCONF2,
+  COP0Sel_SRSCONF3, COP0Sel_SRSCONF4, COP0Sel_PWCTL, COP0Sel_HWRENA,
+  COP0Sel_BADVADDR, COP0Sel_BADINST, COP0Sel_BADINSTRP, COP0Sel_BADINSTRX,
+  COP0Sel_COUNT, COP0Sel_ENTRYHI, COP0Sel_GUESTCTL1, COP0Sel_GUESTCTL2,
+  COP0Sel_GUESTCTL3, COP0Sel_COMPARE, COP0Sel_GUESTCTL0EXT, COP0Sel_STATUS,
+  COP0Sel_INTCTL, COP0Sel_SRSCTL, COP0Sel_SRSMAP, COP0Sel_VIEW_IPL,
+  COP0Sel_SRSMAP2, COP0Sel_GUESTCTL0, COP0Sel_GTOFFSET, COP0Sel_CAUSE,
+  COP0Sel_VIEW_RIPL, COP0Sel_NESTEDEXC, COP0Sel_EPC, COP0Sel_NESTEDEPC,
+  COP0Sel_PRID, COP0Sel_EBASE, COP0Sel_CDMMBASE, COP0Sel_CMGCRBASE,
+  COP0Sel_BEVVA, COP0Sel_CONFIG, COP0Sel_CONFIG1, COP0Sel_CONFIG2,
+  COP0Sel_CONFIG3, COP0Sel_CONFIG4, COP0Sel_CONFIG5, COP0Sel_LLADDR,
+  COP0Sel_MAAR, COP0Sel_MAARI, COP0Sel_WATCHLO0, COP0Sel_WATCHLO1,
+  COP0Sel_WATCHLO2, COP0Sel_WATCHLO3, COP0Sel_WATCHLO4, COP0Sel_WATCHLO5,
+  COP0Sel_WATCHLO6, COP0Sel_WATCHLO7, COP0Sel_WATCHLO8, COP0Sel_WATCHLO9,
+  COP0Sel_WATCHLO10, COP0Sel_WATCHLO11, COP0Sel_WATCHLO12, COP0Sel_WATCHLO13,
+  COP0Sel_WATCHLO14, COP0Sel_WATCHLO15, COP0Sel_WATCHHI0, COP0Sel_WATCHHI1,
+  COP0Sel_WATCHHI2, COP0Sel_WATCHHI3, COP0Sel_WATCHHI4, COP0Sel_WATCHHI5,
+  COP0Sel_WATCHHI6, COP0Sel_WATCHHI7, COP0Sel_WATCHHI8, COP0Sel_WATCHHI9,
+  COP0Sel_WATCHHI10, COP0Sel_WATCHHI11, COP0Sel_WATCHHI12, COP0Sel_WATCHHI13,
+  COP0Sel_WATCHHI14, COP0Sel_WATCHHI15, COP0Sel_XCONTEXT, COP0Sel_DEBUG,
+  COP0Sel_TRACECONTROL, COP0Sel_TRACECONTROL2, COP0Sel_USERTRACEDATA1,
+  COP0Sel_TRACEIBPC, COP0Sel_TRACEDBPC, COP0Sel_DEBUG2, COP0Sel_DEPC,
+  COP0Sel_TRACECONTROL3, COP0Sel_USERTRACEDATA2, COP0Sel_PERFCTL0,
+  COP0Sel_PERFCNT0, COP0Sel_PERFCTL1, COP0Sel_PERFCNT1, COP0Sel_PERFCTL2,
+  COP0Sel_PERFCNT2, COP0Sel_PERFCTL3, COP0Sel_PERFCNT3, COP0Sel_PERFCTL4,
+  COP0Sel_PERFCNT4, COP0Sel_PERFCTL5, COP0Sel_PERFCNT5, COP0Sel_PERFCTL6,
+  COP0Sel_PERFCNT6, COP0Sel_PERFCTL7, COP0Sel_PERFCNT7, COP0Sel_ERRCTL,
+  COP0Sel_CACHEERR, COP0Sel_ITAGLO, COP0Sel_IDATALO, COP0Sel_DTAGLO,
+  COP0Sel_DDATALO, COP0Sel_ITAGHI, COP0Sel_IDATAHI, COP0Sel_DTAGHI,
+  COP0Sel_DDATAHI, COP0Sel_ERROREPC, COP0Sel_DESAVE, COP0Sel_KSCRATCH1,
+  COP0Sel_KSCRATCH2, COP0Sel_KSCRATCH3, COP0Sel_KSCRATCH4, COP0Sel_KSCRATCH5,
+  COP0Sel_KSCRATCH6)>;
+
+def COP0Sel : COP0SelRegClassNM<[i32]>, Unallocatable;
+
+def GPRNM32_TAIL : RegisterClass<"Mips", [i32], 32, (add
+  // Not preserved across procedure calls
+  T4_NM, T5_NM,
+  // Return Values and Arguments
+  A0_NM, A1_NM, A2_NM, A3_NM, A4_NM, A5_NM, A6_NM, A7_NM,
+  // Not preserved across procedure calls
+  T0_NM, T1_NM, T2_NM, T3_NM,
+  // Not preserved across procedure calls
+  T8_NM, T9_NM)>;
+
+// nanoMIPS "gpr3" register encoding type.
+def GPRNM3 : RegisterClass<"Mips", [i32], 32, (add
+  // Callee save
+  S0_NM, S1_NM, S2_NM, S3_NM,
+  // Return Values and Arguments
+  A0_NM, A1_NM, A2_NM, A3_NM)>;
+
+// nanoMIPS "gpr3.zero" register encoding type.
+def GPRNM3Z : RegisterClass<"Mips", [i32], 32, (add
+  // Reserved
+  ZERO_NM,
+  // Callee save
+  S1_NM, S2_NM, S3_NM,
+  // Return Values and Arguments
+  A0_NM, A1_NM, A2_NM, A3_NM)>;
+
+// nanoMIPS "gpr4x4" register encoding type.
+def GPRNM4 : RegisterClass<"Mips", [i32], 32, (add
+  // Return Values and Arguments
+  A4_NM, A5_NM, A6_NM, A7_NM, A0_NM, A1_NM, A2_NM, A3_NM,
+  // Callee save
+  S0_NM, S1_NM, S2_NM, S3_NM, S4_NM, S5_NM, S6_NM, S7_NM)>;
+
+// nanoMIPS "gpr4x4.zero" register encoding type.
+def GPRNM4Z : RegisterClass<"Mips", [i32], 32, (add
+  // Return Values and Arguments
+  A4_NM, A5_NM, A6_NM,
+  // Reserved
+  ZERO_NM,
+  // Return Values and Arguments
+  A0_NM, A1_NM, A2_NM, A3_NM,
+  // Callee save
+  S0_NM, S1_NM, S2_NM, S3_NM, S4_NM, S5_NM, S6_NM, S7_NM)>;
+
+// nanoMIPS non-zero gpr register encoding type.
+def GPRNM32NZ : RegisterClass<"Mips", [i32], 32, (add
+  // Reserved
+  AT_NM,
+  // Not preserved across procedure calls
+  T4_NM, T5_NM,
+  // Return Values and Arguments
+  A0_NM, A1_NM, A2_NM, A3_NM, A4_NM, A5_NM, A6_NM, A7_NM,
+  // Not preserved across procedure calls
+  T0_NM, T1_NM, T2_NM, T3_NM,
+  // Callee save
+  S0_NM, S1_NM, S2_NM, S3_NM, S4_NM, S5_NM, S6_NM, S7_NM,
+  // Not preserved across procedure calls
+  T8_NM, T9_NM,
+  // Reserved
+  K0_NM, K1_NM, GP_NM, SP_NM, FP_NM, RA_NM)>;
+
+// nanoMIPS: Stack pointer, global pointer and return address classes for
+// instructions that are limited to a single register
+def GPRNMSP : RegisterClass<"Mips", [i32], 32, (add SP_NM)>, Unallocatable;
+
+def GPRNMGP : RegisterClass<"Mips", [i32], 32, (add GP_NM)>, Unallocatable;
+
+def GPRNMRA : RegisterClass<"Mips", [i32], 32, (add RA_NM)>, Unallocatable;
+
+// nanoMIPS "gpr2.reg1" & "gpr2.reg2" register encoding types.
+def GPRNM2R1 : RegisterClass<"Mips", [i32], 32, (add
----------------
FlyGoat wrote:

Maybe use `RegisterTuples` for 2R Oprands?

https://github.com/llvm/llvm-project/pull/223032