[llvm] [AMDGPU] Ignore debug instructions in GPR-index scan distance (PR #224279)
Yongqiang Tian via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 17 05:27:35 PDT 2026
https://github.com/yqtian-se created https://github.com/llvm/llvm-project/pull/224279
## Summary
- exclude debug instructions from `SIPreEmitPeephole`'s bounded search for redundant GPR-index mode transitions
- add a verifier-enabled MIR regression test where `DBG_VALUE` instructions previously exhausted the search distance and left an extra `S_SET_GPR_IDX_OFF`/`S_SET_GPR_IDX_ON` pair
## Testing
- `python3 llvm/utils/update_mir_test_checks.py --llc-binary build/bin/llc llvm/test/CodeGen/AMDGPU/set-gpr-idx-debug-instr.mir`
- `llvm-lit -sv llvm/test/CodeGen/AMDGPU/set-gpr-idx-debug-instr.mir llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir`
- `ninja check-llvm-codegen-amdgpu` (5057 passed, 6 expectedly failed)
- confirmed the fixed-behavior test fails on the unmodified build
- confirmed the original reproducer changes from 16/24-byte `.text` sections to identical 16-byte sections after the fix
Fixes #224271
AI disclosure: This patch was developed with OpenAI Codex 5.6 Sol and reviewed with Claude.
>From 0d05ce5dfd1ac2f7be08740686fdbe999218a0c3 Mon Sep 17 00:00:00 2001
From: Yongqiang Tian <yqtian668 at gmail.com>
Date: Thu, 17 Sep 2026 12:26:39 +0000
Subject: [PATCH] [AMDGPU] Ignore debug instructions in GPR-index scan distance
SIPreEmitPeephole limits the search for redundant GPR-index mode
transitions to 20 instructions. The raw instruction counter currently
includes debug instructions, so sufficiently many DBG_VALUEs can prevent
the second transition from being optimized away.
Skip debug instructions before updating the search counter. Add a MIR
regression test covering the boundary-crossing case.
Fixes #224271
Assisted-by: OpenAI Codex 5.6 Sol, co-reviewed by Claude and Yongqiang Tian.
---
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp | 2 +
.../AMDGPU/set-gpr-idx-debug-instr.mir | 55 +++++++++++++++++++
2 files changed, 57 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/set-gpr-idx-debug-instr.mir
diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
index 9b67cdd6be6f4..53213846d6271 100644
--- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
@@ -904,6 +904,8 @@ bool SIPreEmitPeephole::run(MachineFunction &MF, MachineLoopInfo *LoopInfo) {
// Note: this needs to work on bundles as S_SET_GPR_IDX* instructions
// may be bundled with the instructions they modify.
for (auto &MI : make_early_inc_range(MBB.instrs())) {
+ if (MI.isDebugInstr())
+ continue;
if (Count == Threshold)
SetGPRMI = nullptr;
else
diff --git a/llvm/test/CodeGen/AMDGPU/set-gpr-idx-debug-instr.mir b/llvm/test/CodeGen/AMDGPU/set-gpr-idx-debug-instr.mir
new file mode 100644
index 0000000000000..52b27b3e8f744
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/set-gpr-idx-debug-instr.mir
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu9.00 -run-pass si-pre-emit-peephole -verify-machineinstrs -o - %s | FileCheck %s -implicit-check-not=S_SET_GPR_IDX
+
+---
+name: debug_value_in_between
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: debug_value_in_between
+ ; CHECK: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0
+ ; CHECK-NEXT: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ ; CHECK-NEXT: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
+ S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ DBG_VALUE $noreg, 0
+ $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
+ S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
+ $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+ S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
+...
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