[llvm] [RISCV] Fix incorrect vscale addition folding (PR #224220)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: FoolgryGamer

<details>
<summary>Changes</summary>

Fix https://github.com/llvm/llvm-project/issues/222933

---
Full diff: https://github.com/llvm/llvm-project/pull/224220.diff


1 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+4-3) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d4a7403a6b25f..b7d19e4a55a28 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3325,9 +3325,10 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
   }
 
   // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
-  if (N0.getOpcode() == ISD::ADD &&
-      N0.getOperand(1).getOpcode() == ISD::VSCALE &&
-      N1.getOpcode() == ISD::VSCALE) {
+  if ((N0.getOpcode() == ISD::ADD &&
+       N0.getOperand(1).getOpcode() == ISD::VSCALE &&
+       N1.getOpcode() == ISD::VSCALE) &&
+      N0.hasOneUse()) {
     const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
     const APInt &VS1 = N1->getConstantOperandAPInt(0);
     SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1);

``````````

</details>


https://github.com/llvm/llvm-project/pull/224220