[llvm] [RISCV] Fix incorrect vscale addition folding (PR #224220)

[via llvm-commits]

https://github.com/FoolgryGamer created https://github.com/llvm/llvm-project/pull/224220

Fix https://github.com/llvm/llvm-project/issues/222933

>From 449d4b8f12b13a28b81e64e6ad10ecb5f9fd4c2d Mon Sep 17 00:00:00 2001
From: FoolgryGamer <1353470175 at qq.com>
Date: Thu, 17 Sep 2026 15:37:31 +0800
Subject: [PATCH] [RISCV] Fix incorrect vscale addition folding

The DAGCombiner was folding (A + vscale(C1)) + vscale(C2) into
A + vscale(C1+C2) even when the inner add had multiple uses, which
could introduce an extra add instruction on RISC-V.

This patch restricts the fold to the case where the inner add has
only one use.

Fixes #222933
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d4a7403a6b25f..b7d19e4a55a28 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3325,9 +3325,10 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
   }
 
   // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
-  if (N0.getOpcode() == ISD::ADD &&
-      N0.getOperand(1).getOpcode() == ISD::VSCALE &&
-      N1.getOpcode() == ISD::VSCALE) {
+  if ((N0.getOpcode() == ISD::ADD &&
+       N0.getOperand(1).getOpcode() == ISD::VSCALE &&
+       N1.getOpcode() == ISD::VSCALE) &&
+      N0.hasOneUse()) {
     const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
     const APInt &VS1 = N1->getConstantOperandAPInt(0);
     SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1);