[llvm] fd2f003 - [SLP][NFC]Add a test with missed vectorization because of instcount check, NFC

[via llvm-commits]

Author: Alexey Bataev
Date: 2026-09-16T12:47:34-04:00
New Revision: fd2f003b399675d0e6cf135ebc3b97cb138b699d

URL: https://github.com/llvm/llvm-project/commit/fd2f003b399675d0e6cf135ebc3b97cb138b699d
DIFF: https://github.com/llvm/llvm-project/commit/fd2f003b399675d0e6cf135ebc3b97cb138b699d.diff

LOG: [SLP][NFC]Add a test with missed vectorization because of instcount check, NFC



Reviewers: 

Pull Request: https://github.com/llvm/llvm-project/pull/224074

Added: 
    llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-inst-count.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-inst-count.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-inst-count.ll
new file mode 100644
index 0000000000000..5e043e5034e54
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-inst-count.ll
@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu -mcpu=olympus < %s | FileCheck %s
+;
+; The splat gather subtree built for the broadcast scalars would tip the VF=2
+; vector-vs-scalar instruction count veto and reject the whole store chain. It
+; must be dropped during trimming so the two adjacent stores are still
+; vectorized as a single <2 x double> store.
+;
+define void @store_chain_splat_subtree(ptr %matrix, double %a) {
+; CHECK-LABEL: @store_chain_splat_subtree(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call double @llvm.fmuladd.f64(double [[A1:%.*]], double 0.000000e+00, double 0.000000e+00)
+; CHECK-NEXT:    [[A:%.*]] = tail call double @llvm.fmuladd.f64(double [[A1]], double 0.000000e+00, double 0.000000e+00)
+; CHECK-NEXT:    [[MUL0:%.*]] = fmul double [[A]], 0.000000e+00
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call double @llvm.fmuladd.f64(double [[TMP3]], double 0.000000e+00, double [[MUL0]])
+; CHECK-NEXT:    [[TMP6:%.*]] = tail call double @llvm.fmuladd.f64(double [[TMP2]], double 0.000000e+00, double 0.000000e+00)
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr i8, ptr [[MATRIX:%.*]], i64 24
+; CHECK-NEXT:    store double [[TMP6]], ptr [[GEP0]], align 8
+; CHECK-NEXT:    [[MUL1:%.*]] = fmul double [[A]], 0.000000e+00
+; CHECK-NEXT:    [[TMP4:%.*]] = tail call double @llvm.fmuladd.f64(double [[TMP3]], double 0.000000e+00, double [[MUL1]])
+; CHECK-NEXT:    [[TMP5:%.*]] = tail call double @llvm.fmuladd.f64(double [[TMP4]], double 0.000000e+00, double 0.000000e+00)
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 32
+; CHECK-NEXT:    store double [[TMP5]], ptr [[GEP1]], align 8
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = tail call double @llvm.fmuladd.f64(double %a, double 0.000000e+00, double 0.000000e+00)
+  %1 = tail call double @llvm.fmuladd.f64(double %a, double 0.000000e+00, double 0.000000e+00)
+  %mul0 = fmul double %1, 0.000000e+00
+  %2 = tail call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double %mul0)
+  %3 = tail call double @llvm.fmuladd.f64(double %2, double 0.000000e+00, double 0.000000e+00)
+  %gep0 = getelementptr i8, ptr %matrix, i64 24
+  store double %3, ptr %gep0, align 8
+  %mul1 = fmul double %1, 0.000000e+00
+  %4 = tail call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double %mul1)
+  %5 = tail call double @llvm.fmuladd.f64(double %4, double 0.000000e+00, double 0.000000e+00)
+  %gep1 = getelementptr i8, ptr %matrix, i64 32
+  store double %5, ptr %gep1, align 8
+  ret void
+}
+
+declare double @llvm.fmuladd.f64(double, double, double)