[llvm] CodeGen: Add getInlineAsmMemoryOperandRegClass (PR #223959)
via llvm-commits
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Wed Sep 16 02:55:54 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
Replace the use of getPointerRegClass to determine the register
class from an asm memory constraint, working to delete it. When
there are multiple pointer types there can't be just a single
answer.
Co-authored-by: Claude (Opus 4.8) <noreply@<!-- -->anthropic.com>
---
Full diff: https://github.com/llvm/llvm-project/pull/223959.diff
9 Files Affected:
- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+7)
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+4-3)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.h (+5)
- (modified) llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (+3-2)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (+6)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.h (+3)
- (modified) llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (+2-1)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.h (+5)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 260cf794c731f..95bdd660061f8 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -164,6 +164,13 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
virtual const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID,
unsigned OpNum) const;
+ /// Return the register class to use for the register operand of an inline asm
+ /// memory operand with constraint \p C.
+ virtual const TargetRegisterClass *
+ getInlineAsmMemoryOperandRegClass(InlineAsm::ConstraintCode C) const {
+ llvm_unreachable("target did not implement memory operand support);
+ }
+
/// Returns true if MI is an instruction we are unable to reason about
/// (like a call or something with unmodeled side effects).
virtual bool isGlobalMemoryObject(const MachineInstr *MI) const;
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 1c0f4d694fa3d..ad15404689f5a 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1037,7 +1037,7 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx,
// Assume that all registers in a memory operand are pointers.
if (F.isMemKind())
- return TRI->getPointerRegClass();
+ return TII->getInlineAsmMemoryOperandRegClass(F.getMemoryConstraintID());
return nullptr;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 531478517ef9a..7fef695e4edad 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -747,9 +747,10 @@ bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
case InlineAsm::ConstraintCode::o:
case InlineAsm::ConstraintCode::Q:
// We need to make sure that this one operand does not end up in XZR, thus
- // require the address to be in a PointerRegClass register.
- const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
- const TargetRegisterClass *TRC = TRI->getPointerRegClass();
+ // require the address to be in a pointer register.
+ const TargetInstrInfo *TII = Subtarget->getInstrInfo();
+ const TargetRegisterClass *TRC =
+ TII->getInlineAsmMemoryOperandRegClass(ConstraintID);
SDLoc dl(Op);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
SDValue NewOp =
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 8d913f111b44c..99e0142824d43 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -189,6 +189,11 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
/// always be able to get register info as well (through this method).
const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
+ const TargetRegisterClass *getInlineAsmMemoryOperandRegClass(
+ InlineAsm::ConstraintCode C) const override {
+ return &AArch64::GPR64spRegClass;
+ }
+
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
bool isAsCheapAsAMove(const MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index bb117d8f3fbbd..ec276e9880f10 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -400,8 +400,9 @@ namespace {
case InlineAsm::ConstraintCode::Zy:
// We need to make sure that this one operand does not end up in r0
// (because we might end up lowering this as 0(%op)).
- const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
- const TargetRegisterClass *TRC = TRI->getPointerRegClass(/*Kind=*/1);
+ const TargetInstrInfo *TII = Subtarget->getInstrInfo();
+ const TargetRegisterClass *TRC =
+ TII->getInlineAsmMemoryOperandRegClass(ConstraintID);
SDLoc dl(Op);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
SDValue NewOp =
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 97a1d92e8bb1e..a4be03cbb3e42 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -94,6 +94,12 @@ PPCInstrInfo::PPCInstrInfo(const PPCSubtarget &STI)
STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
Subtarget(STI), RI(STI.getTargetMachine()) {}
+const TargetRegisterClass *PPCInstrInfo::getInlineAsmMemoryOperandRegClass(
+ InlineAsm::ConstraintCode C) const {
+ return Subtarget.isPPC64() ? &PPC::G8RC_NOX0RegClass
+ : &PPC::GPRC_NOR0RegClass;
+}
+
/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
/// this target when scheduling the DAG.
ScheduleHazardRecognizer *
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index c8a747ac829ec..28687ffc5338c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -381,6 +381,9 @@ class PPCInstrInfo : public PPCGenInstrInfo {
///
const PPCRegisterInfo &getRegisterInfo() const { return RI; }
+ const TargetRegisterClass *
+ getInlineAsmMemoryOperandRegClass(InlineAsm::ConstraintCode C) const override;
+
bool isXFormMemOp(unsigned Opcode) const {
return get(Opcode).TSFlags & PPCII::XFormMemOp;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index cb09611db7d16..9ab0a4a7f2368 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -1908,7 +1908,8 @@ bool SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand(
if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) {
const TargetRegisterClass *TRC =
- Subtarget->getRegisterInfo()->getPointerRegClass();
+ Subtarget->getInstrInfo()->getInlineAsmMemoryOperandRegClass(
+ ConstraintID);
SDLoc DL(Base);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32);
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index d423fda990294..452671443bb12 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -309,6 +309,11 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
// Return the SystemZRegisterInfo, which this class owns.
const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
+ const TargetRegisterClass *getInlineAsmMemoryOperandRegClass(
+ InlineAsm::ConstraintCode C) const override {
+ return &SystemZ::ADDR64BitRegClass;
+ }
+
// Return the size in bytes of MI.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
``````````
</details>
https://github.com/llvm/llvm-project/pull/223959
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