[llvm] [test][AggressiveInstCombine] Test type legality handling in `TruncInstCombine` (NFC) (PR #222930)

[Ömer Sinan Ağacan via llvm-commits]

https://github.com/osa1 updated https://github.com/llvm/llvm-project/pull/222930

>From 30de23270e5f3584e54d4b601899fc8040295b5a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omer at osa1.net>
Date: Fri, 11 Sep 2026 12:31:59 +0100
Subject: [PATCH 1/2] [test][AggressiveInstCombine] Test type legality handling
 in `TruncInstCombine` (NFC)

I noticed that this block of code that checks type legality in
`TruncInstCombine::getMinBitWidth` is not tested:

  else { // MinBitWidth == TruncBitWidth
    // In this case the expression can be evaluated with the trunc instruction
    // destination type, and trunc instruction can be omitted. However, we
    // should not perform the evaluation if the original type is a legal scalar
    // type and the target type is illegal.
    bool FromLegal = MinBitWidth == 1 || DL.isLegalInteger(OrigBitWidth);
    bool ToLegal = MinBitWidth == 1 || DL.isLegalInteger(MinBitWidth);
    if (!DstTy->isVectorTy() && FromLegal && !ToLegal)
      return OrigBitWidth;
  }

This commit adds tests.
---
 .../trunc_illegal_type.ll                     | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll

diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll
new file mode 100644
index 0000000000000..c643006d2a161
--- /dev/null
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll
@@ -0,0 +1,61 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=aggressive-instcombine -S | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; Check type legality handling in `TruncInstCombine::getMinBitWidth`.
+
+; Illegal truncate target, don't reduce.
+define i24 @illegal_dst_legal_src(i24 %a, i24 %b) {
+; CHECK-LABEL: @illegal_dst_legal_src(
+; CHECK-NEXT:    [[ZA:%.*]] = zext i24 [[A:%.*]] to i32
+; CHECK-NEXT:    [[ZB:%.*]] = zext i24 [[B:%.*]] to i32
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[ZA]], [[ZB]]
+; CHECK-NEXT:    [[T:%.*]] = trunc i32 [[ADD]] to i24
+; CHECK-NEXT:    ret i24 [[T]]
+;
+  %za = zext i24 %a to i32
+  %zb = zext i24 %b to i32
+  %add = add i32 %za, %zb
+  %t = trunc i32 %add to i24
+  ret i24 %t
+}
+
+; Source and target types are both legal, reduce.
+define i16 @legal_dst_legal_src(i16 %a, i16 %b) {
+; CHECK-LABEL: @legal_dst_legal_src(
+; CHECK-NEXT:    [[ADD:%.*]] = add i16 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret i16 [[ADD]]
+;
+  %za = zext i16 %a to i32
+  %zb = zext i16 %b to i32
+  %add = add i32 %za, %zb
+  %t = trunc i32 %add to i16
+  ret i16 %t
+}
+
+; Both source and target are illegal, reduce.
+define i24 @illegal_dst_illegal_src(i24 %a, i24 %b) {
+; CHECK-LABEL: @illegal_dst_illegal_src(
+; CHECK-NEXT:    [[ADD:%.*]] = add i24 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret i24 [[ADD]]
+;
+  %za = zext i24 %a to i48
+  %zb = zext i24 %b to i48
+  %add = add i48 %za, %zb
+  %t = trunc i48 %add to i24
+  ret i24 %t
+}
+
+; The legality check only applies to scalars, vectors are still reduced.
+define <4 x i24> @illegal_dst_legal_src_vec(<4 x i24> %a, <4 x i24> %b) {
+; CHECK-LABEL: @illegal_dst_legal_src_vec(
+; CHECK-NEXT:    [[ADD:%.*]] = add <4 x i24> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <4 x i24> [[ADD]]
+;
+  %za = zext <4 x i24> %a to <4 x i32>
+  %zb = zext <4 x i24> %b to <4 x i32>
+  %add = add <4 x i32> %za, %zb
+  %t = trunc <4 x i32> %add to <4 x i24>
+  ret <4 x i24> %t
+}

>From 2b6a80561547b6e893e2c5e40a044d3930fb5990 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=96mer=20Sinan=20A=C4=9Facan?= <omer at osa1.net>
Date: Wed, 16 Sep 2026 08:50:26 +0100
Subject: [PATCH 2/2] i1 tests

---
 .../trunc_illegal_type.ll                     | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll
index c643006d2a161..322e97e6ea81c 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_illegal_type.ll
@@ -59,3 +59,34 @@ define <4 x i24> @illegal_dst_legal_src_vec(<4 x i24> %a, <4 x i24> %b) {
   %t = trunc <4 x i32> %add to <4 x i24>
   ret <4 x i24> %t
 }
+
+; As a special case, i1 is always considered legal. We allow truncating both
+; legal and illegal types to i1.
+
+define i1 @legal_to_i1(i24 %a, i24 %b) {
+; CHECK-LABEL: @legal_to_i1(
+; CHECK-NEXT:    [[ZA:%.*]] = trunc i24 [[A:%.*]] to i1
+; CHECK-NEXT:    [[ZB:%.*]] = trunc i24 [[B:%.*]] to i1
+; CHECK-NEXT:    [[ADD:%.*]] = add i1 [[ZA]], [[ZB]]
+; CHECK-NEXT:    ret i1 [[ADD]]
+;
+  %za = zext i24 %a to i32
+  %zb = zext i24 %b to i32
+  %add = add i32 %za, %zb
+  %t = trunc i32 %add to i1
+  ret i1 %t
+}
+
+define i1 @illegal_to_i1(i24 %a, i24 %b) {
+; CHECK-LABEL: @illegal_to_i1(
+; CHECK-NEXT:    [[ZA:%.*]] = trunc i24 [[A:%.*]] to i1
+; CHECK-NEXT:    [[ZB:%.*]] = trunc i24 [[B:%.*]] to i1
+; CHECK-NEXT:    [[ADD:%.*]] = add i1 [[ZA]], [[ZB]]
+; CHECK-NEXT:    ret i1 [[ADD]]
+;
+  %za = zext i24 %a to i33
+  %zb = zext i24 %b to i33
+  %add = add i33 %za, %zb
+  %t = trunc i33 %add to i1
+  ret i1 %t
+}