[llvm] 10c3714 - [RISCV] Do not verify size for some Xqci instructions (#223913)

[via llvm-commits]

Author: Sudharsan Veeravalli
Date: 2026-09-16T13:17:39+05:30
New Revision: 10c37146ce3b3f850fb9afa9f00d02eb860ff237

URL: https://github.com/llvm/llvm-project/commit/10c37146ce3b3f850fb9afa9f00d02eb860ff237
DIFF: https://github.com/llvm/llvm-project/commit/10c37146ce3b3f850fb9afa9f00d02eb860ff237.diff

LOG: [RISCV] Do not verify size for some Xqci instructions (#223913)

After instruction size verification was enabled by default in
https://github.com/llvm/llvm-project/pull/221687/ we were running into
crashes for certain 48-bit Xqci instructions. This was happening because
we have compress patterns for these 48-bit instructions to compress them
into 32-bit instructions which `getInstSizeInBytes` was not taking into
account.

The crash looks like:

```
Size mismatch for: QC_E_SW $x0, $x14, 0 :: (store (s32) into %stack.0)
Expected maximum size: 2
Actual size: 4
```

Do not verify size for such instructions until we can return the correct
size for them.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 559f6f4cb6069..3f860c93e10b9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -333,6 +333,43 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   bool isHighLatencyDef(int Opc) const override;
 
+  InstSizeVerifyMode
+  getInstSizeVerifyMode(const MachineInstr &MI) const override {
+    // FIXME: These Xqci instructions can compress from a 6 byte to a 4 byte
+    // instruction but getInstSizeInBytes unilaterally returns 2 for any
+    // compressible instruction.
+    switch (MI.getOpcode()) {
+    case RISCV::QC_E_LW:
+    case RISCV::QC_E_LB:
+    case RISCV::QC_E_LH:
+    case RISCV::QC_E_LBU:
+    case RISCV::QC_E_LHU:
+    case RISCV::QC_E_SW:
+    case RISCV::QC_E_SB:
+    case RISCV::QC_E_SH:
+    case RISCV::QC_E_JAL:
+    case RISCV::QC_E_J:
+    case RISCV::QC_E_LI:
+    case RISCV::QC_E_ADDI:
+    case RISCV::QC_E_ANDI:
+    case RISCV::QC_E_ORI:
+    case RISCV::QC_E_XORI:
+    case RISCV::QC_E_ADDAI:
+    case RISCV::QC_E_ANDAI:
+    case RISCV::QC_E_ORAI:
+    case RISCV::QC_E_XORAI:
+    case RISCV::QC_E_BEQI:
+    case RISCV::QC_E_BNEI:
+    case RISCV::QC_E_BLTI:
+    case RISCV::QC_E_BGEUI:
+    case RISCV::QC_E_BLTUI:
+    case RISCV::QC_E_BGEI:
+      return InstSizeVerifyMode::NoVerify;
+    default:
+      return InstSizeVerifyMode::AllowOverEstimate;
+    }
+  }
+
   /// Return true if \p MI is a COPY to a vector register of a specific \p LMul,
   /// or any kind of vector registers when \p LMul is zero.
   bool isVRegCopy(const MachineInstr *MI, unsigned LMul = 0) const;