[llvm] [AMDGPU] Skip volatile atomics in the atomic optimizer (PR #223927)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 16 00:04:09 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Arseniy Obolenskiy (aobolensk)
<details>
<summary>Changes</summary>
Folding a wavefront into one atomic changes the number of volatile operations, which is not allowed
---
Patch is 59.61 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223927.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp (+5-1)
- (added) llvm/test/CodeGen/AMDGPU/atomic-optimizer-volatile.ll (+178)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll (+102-102)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_iterative_scan.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/mubuf.ll (+1-1)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
index af87a6ee92ef8..18c7cac7df885 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
@@ -183,7 +183,7 @@ static bool isLegalCrossLaneType(Type *Ty) {
}
void AMDGPUAtomicOptimizerImpl::visitAtomicRMWInst(AtomicRMWInst &I) {
- if (I.getType()->isVectorTy())
+ if (I.getType()->isVectorTy() || I.isVolatile())
return;
// Early exit for unhandled address space atomic instructions.
@@ -318,6 +318,10 @@ void AMDGPUAtomicOptimizerImpl::visitIntrinsicInst(IntrinsicInst &I) {
break;
}
+ auto *Aux = cast<ConstantInt>(I.getArgOperand(I.arg_size() - 1));
+ if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE)
+ return;
+
const unsigned ValIdx = 0;
const bool ValDivergent = UA.isDivergentAtUse(I.getOperandUse(ValIdx));
diff --git a/llvm/test/CodeGen/AMDGPU/atomic-optimizer-volatile.ll b/llvm/test/CodeGen/AMDGPU/atomic-optimizer-volatile.ll
new file mode 100644
index 0000000000000..faa4f1f20bf18
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/atomic-optimizer-volatile.ll
@@ -0,0 +1,178 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes='amdgpu-atomic-optimizer<strategy=iterative>,verify<domtree>' %s | FileCheck --check-prefix=IR %s
+; RUN: opt -S -mtriple=amdgpu9.00-amd-amdhsa -passes='amdgpu-atomic-optimizer<strategy=dpp>,verify<domtree>' %s | FileCheck --check-prefix=IR %s
+
+; Folding a wavefront into a single atomic would change the number of volatile
+; operations, so these must be left alone.
+
+define amdgpu_kernel void @volatile_global(ptr addrspace(1) %out, ptr addrspace(1) %inout) {
+; IR-LABEL: define amdgpu_kernel void @volatile_global(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*:]]
+; IR-NEXT: [[OLD:%.*]] = atomicrmw volatile add ptr addrspace(1) [[INOUT]], i32 5 syncscope("agent") acq_rel, align 4
+; IR-NEXT: store i32 [[OLD]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = atomicrmw volatile add ptr addrspace(1) %inout, i32 5 syncscope("agent") acq_rel
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @volatile_local(ptr addrspace(1) %out, ptr addrspace(3) %inout) {
+; IR-LABEL: define amdgpu_kernel void @volatile_local(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(3) [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*:]]
+; IR-NEXT: [[OLD:%.*]] = atomicrmw volatile add ptr addrspace(3) [[INOUT]], i32 5 acq_rel, align 4
+; IR-NEXT: store i32 [[OLD]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = atomicrmw volatile add ptr addrspace(3) %inout, i32 5 acq_rel
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+; A divergent value is the only case where the iterative and DPP strategies
+; differ, so cover it too.
+define amdgpu_kernel void @volatile_global_divergent(ptr addrspace(1) %out, ptr addrspace(1) %inout) {
+; IR-LABEL: define amdgpu_kernel void @volatile_global_divergent(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*:]]
+; IR-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; IR-NEXT: [[OLD:%.*]] = atomicrmw volatile add ptr addrspace(1) [[INOUT]], i32 [[ID]] syncscope("agent") acq_rel, align 4
+; IR-NEXT: store i32 [[OLD]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %id = call i32 @llvm.amdgcn.workitem.id.x()
+ %old = atomicrmw volatile add ptr addrspace(1) %inout, i32 %id syncscope("agent") acq_rel
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+; Negative control: the same atomic without the volatile marker must be folded.
+define amdgpu_kernel void @nonvolatile_global(ptr addrspace(1) %out, ptr addrspace(1) %inout) {
+; IR-LABEL: define amdgpu_kernel void @nonvolatile_global(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*]]:
+; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
+; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
+; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
+; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
+; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
+; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
+; IR-NEXT: [[TMP8:%.*]] = mul i32 5, [[TMP7]]
+; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
+; IR-NEXT: br i1 [[TMP9]], label %[[BB10:.*]], label %[[BB12:.*]]
+; IR: [[BB10]]:
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[INOUT]], i32 [[TMP8]] syncscope("agent") acq_rel, align 4
+; IR-NEXT: br label %[[BB12]]
+; IR: [[BB12]]:
+; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, %[[ENTRY]] ], [ [[TMP11]], %[[BB10]] ]
+; IR-NEXT: [[TMP14:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP13]])
+; IR-NEXT: [[TMP15:%.*]] = mul i32 5, [[TMP5]]
+; IR-NEXT: [[TMP16:%.*]] = add i32 [[TMP14]], [[TMP15]]
+; IR-NEXT: store i32 [[TMP16]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = atomicrmw add ptr addrspace(1) %inout, i32 5 syncscope("agent") acq_rel
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+; cachepolicy bit 31 is the volatile flag for buffer atomics. Its operand index
+; differs between the raw and struct forms, and between the rsrc and pointer
+; forms, so cover all four.
+define amdgpu_kernel void @volatile_raw_ptr_buffer(ptr addrspace(1) %out, ptr addrspace(8) %inout) {
+; IR-LABEL: define amdgpu_kernel void @volatile_raw_ptr_buffer(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(8) [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*:]]
+; IR-NEXT: [[OLD:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add.i32(i32 5, ptr addrspace(8) [[INOUT]], i32 0, i32 0, i32 -2147483648)
+; IR-NEXT: store i32 [[OLD]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 -2147483648)
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @volatile_struct_ptr_buffer(ptr addrspace(1) %out, ptr addrspace(8) %inout) {
+; IR-LABEL: define amdgpu_kernel void @volatile_struct_ptr_buffer(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(8) [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*:]]
+; IR-NEXT: [[OLD:%.*]] = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32 5, ptr addrspace(8) [[INOUT]], i32 0, i32 0, i32 0, i32 -2147483648)
+; IR-NEXT: store i32 [[OLD]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0, i32 -2147483648)
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @volatile_raw_buffer(ptr addrspace(1) %out, <4 x i32> inreg %inout) {
+; IR-LABEL: define amdgpu_kernel void @volatile_raw_buffer(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], <4 x i32> inreg [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*:]]
+; IR-NEXT: [[OLD:%.*]] = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 5, <4 x i32> [[INOUT]], i32 0, i32 0, i32 -2147483648)
+; IR-NEXT: store i32 [[OLD]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = call i32 @llvm.amdgcn.raw.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 -2147483648)
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @volatile_struct_buffer(ptr addrspace(1) %out, <4 x i32> inreg %inout) {
+; IR-LABEL: define amdgpu_kernel void @volatile_struct_buffer(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], <4 x i32> inreg [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*:]]
+; IR-NEXT: [[OLD:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 5, <4 x i32> [[INOUT]], i32 0, i32 0, i32 0, i32 -2147483648)
+; IR-NEXT: store i32 [[OLD]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = call i32 @llvm.amdgcn.struct.buffer.atomic.add(i32 5, <4 x i32> %inout, i32 0, i32 0, i32 0, i32 -2147483648)
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
+
+; Negative control: only bit 31 means volatile, so a plain cachepolicy bit must
+; not block the optimization.
+define amdgpu_kernel void @nonvolatile_raw_ptr_buffer(ptr addrspace(1) %out, ptr addrspace(8) %inout) {
+; IR-LABEL: define amdgpu_kernel void @nonvolatile_raw_ptr_buffer(
+; IR-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(8) [[INOUT:%.*]]) {
+; IR-NEXT: [[ENTRY:.*]]:
+; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
+; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
+; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
+; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
+; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
+; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
+; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
+; IR-NEXT: [[TMP8:%.*]] = mul i32 5, [[TMP7]]
+; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
+; IR-NEXT: br i1 [[TMP9]], label %[[BB10:.*]], label %[[BB12:.*]]
+; IR: [[BB10]]:
+; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add.i32(i32 [[TMP8]], ptr addrspace(8) [[INOUT]], i32 0, i32 0, i32 1)
+; IR-NEXT: br label %[[BB12]]
+; IR: [[BB12]]:
+; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, %[[ENTRY]] ], [ [[TMP11]], %[[BB10]] ]
+; IR-NEXT: [[TMP14:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP13]])
+; IR-NEXT: [[TMP15:%.*]] = mul i32 5, [[TMP5]]
+; IR-NEXT: [[TMP16:%.*]] = add i32 [[TMP14]], [[TMP15]]
+; IR-NEXT: store i32 [[TMP16]], ptr addrspace(1) [[OUT]], align 4
+; IR-NEXT: ret void
+;
+entry:
+ %old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 1)
+ store i32 %old, ptr addrspace(1) %out
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll b/llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll
index 4c90b21d0899c..295183b046bf0 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomic-scan.ll
@@ -17,14 +17,14 @@ define amdgpu_kernel void @atomic_add_i32_offset(ptr addrspace(1) %out, i32 %in)
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: ret void
;
entry:
%gep = getelementptr i32, ptr addrspace(1) %out, i64 4
- %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %gep, i32 %in seq_cst
ret void
}
@@ -44,14 +44,14 @@ define amdgpu_kernel void @atomic_add_i32_max_neg_offset(ptr addrspace(1) %out,
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: ret void
;
entry:
%gep = getelementptr i32, ptr addrspace(1) %out, i64 -1024
- %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %gep, i32 %in seq_cst
ret void
}
@@ -71,14 +71,14 @@ define amdgpu_kernel void @atomic_add_i32_soffset(ptr addrspace(1) %out, i32 %in
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: ret void
;
entry:
%gep = getelementptr i32, ptr addrspace(1) %out, i64 9000
- %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %gep, i32 %in seq_cst
ret void
}
@@ -98,7 +98,7 @@ define amdgpu_kernel void @atomic_add_i32_huge_offset(ptr addrspace(1) %out, i32
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: ret void
@@ -106,7 +106,7 @@ define amdgpu_kernel void @atomic_add_i32_huge_offset(ptr addrspace(1) %out, i32
entry:
%gep = getelementptr i32, ptr addrspace(1) %out, i64 47224239175595
- %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %gep, i32 %in seq_cst
ret void
}
@@ -126,7 +126,7 @@ define amdgpu_kernel void @atomic_add_i32_ret_offset(ptr addrspace(1) %out, ptr
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[TMP11]], [[TMP10]] ]
@@ -138,7 +138,7 @@ define amdgpu_kernel void @atomic_add_i32_ret_offset(ptr addrspace(1) %out, ptr
;
entry:
%gep = getelementptr i32, ptr addrspace(1) %out, i64 4
- %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %gep, i32 %in seq_cst
store i32 %val, ptr addrspace(1) %out2
ret void
}
@@ -160,7 +160,7 @@ define amdgpu_kernel void @atomic_add_i32_addr64_offset(ptr addrspace(1) %out, i
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: ret void
@@ -168,7 +168,7 @@ define amdgpu_kernel void @atomic_add_i32_addr64_offset(ptr addrspace(1) %out, i
entry:
%ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4
- %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %gep, i32 %in seq_cst
ret void
}
@@ -189,7 +189,7 @@ define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(ptr addrspace(1) %ou
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[GEP]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[TMP11]], [[TMP10]] ]
@@ -202,7 +202,7 @@ define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(ptr addrspace(1) %ou
entry:
%ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4
- %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %gep, i32 %in seq_cst
store i32 %val, ptr addrspace(1) %out2
ret void
}
@@ -222,13 +222,13 @@ define amdgpu_kernel void @atomic_add_i32(ptr addrspace(1) %out, i32 %in) {
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[OUT:%.*]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[OUT:%.*]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: ret void
;
entry:
- %val = atomicrmw volatile add ptr addrspace(1) %out, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %out, i32 %in seq_cst
ret void
}
@@ -247,7 +247,7 @@ define amdgpu_kernel void @atomic_add_i32_ret(ptr addrspace(1) %out, ptr addrspa
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[OUT:%.*]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[OUT:%.*]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[TMP11]], [[TMP10]] ]
@@ -258,7 +258,7 @@ define amdgpu_kernel void @atomic_add_i32_ret(ptr addrspace(1) %out, ptr addrspa
; IR-NEXT: ret void
;
entry:
- %val = atomicrmw volatile add ptr addrspace(1) %out, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %out, i32 %in seq_cst
store i32 %val, ptr addrspace(1) %out2
ret void
}
@@ -279,14 +279,14 @@ define amdgpu_kernel void @atomic_add_i32_addr64(ptr addrspace(1) %out, i32 %in,
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[PTR]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[PTR]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: ret void
;
entry:
%ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index
- %val = atomicrmw volatile add ptr addrspace(1) %ptr, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %ptr, i32 %in seq_cst
ret void
}
@@ -306,7 +306,7 @@ define amdgpu_kernel void @atomic_add_i32_ret_addr64(ptr addrspace(1) %out, ptr
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
; IR: 10:
-; IR-NEXT: [[TMP11:%.*]] = atomicrmw volatile add ptr addrspace(1) [[PTR]], i32 [[TMP8]] seq_cst, align 4
+; IR-NEXT: [[TMP11:%.*]] = atomicrmw add ptr addrspace(1) [[PTR]], i32 [[TMP8]] seq_cst, align 4
; IR-NEXT: br label [[TMP12]]
; IR: 12:
; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[TMP11]], [[TMP10]] ]
@@ -318,7 +318,7 @@ define amdgpu_kernel void @atomic_add_i32_ret_addr64(ptr addrspace(1) %out, ptr
;
entry:
%ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index
- %val = atomicrmw volatile add ptr addrspace(1) %ptr, i32 %in seq_cst
+ %val = atomicrmw add ptr addrspace(1) %ptr, i32 %in seq_cst
store i32 %val, ptr addrspace(1) %out2
ret void
}
@@ -336,14 +336,14 @@ define amdgpu_kernel void @atomic_and_i32_offset(ptr addrspace(1) %out, i32 %in)
; IR-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
; IR-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP9:%.*]]
; IR: 7:
-; IR-NEXT: [[TMP8:%.*]] = atomicrmw volatile and ptr addrspace(1) [[GEP]], i32 [[IN:%.*]] seq_cst, align 4
+; IR-NEXT: [[TMP8:%.*]] = atomicrmw and ptr addrspace(1) [[GEP]],...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223927
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